Method and apparatus for providing a protection circuit for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Reexamination Certificate

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10985508

ABSTRACT:
Method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

REFERENCES:
patent: 6336208 (2002-01-01), Mohan et al.
patent: 6446242 (2002-09-01), Lien et al.
patent: 6618839 (2003-09-01), Beardslee et al.
patent: 6747480 (2004-06-01), Kaptanoglu et al.
patent: 6874107 (2005-03-01), Lesea
patent: 6876186 (2005-04-01), Gupta
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 2002/0010853 (2002-01-01), Trimberger et al.
patent: 2003/0023912 (2003-01-01), Lesea
patent: 2003/0172363 (2003-09-01), Chauhan et al.
patent: 2004/0024806 (2004-02-01), Jeong et al.
patent: 2005/0040855 (2005-02-01), Boerstler et al.
patent: 2005/0102539 (2005-05-01), Hepner et al.
patent: 2006/0075374 (2006-04-01), McElvain
patent: 2006/0215743 (2006-09-01), Lang et al.
Kahng, A. et al.; “Constraint-Based Watermarking Techniques for Design IP Protection”; Copyright 2002 IEEE; IEEE Transactions on computer-Aided Design of Integrated-Circuits and Systems; vol. 20, No. 10; Oct. 2001; pp. 12361252.
Goering, R.; “‘Digital Signature ’ Technology Aids IP Proection”; EE Times; Mar. 25, 1998; downloaded from http://www.eetimes.com
ews/98/100news/digital.html on Oct. 4, 2007; pp. 1-3.
Jain, A.K. et al.; “Zero Overhead Watermarking Technique for FPGA Designs”; GLSVLSI '03; Apr. 28-29, 2003; Copyright 2003 ACM; pp. 147-152.
Lach, J. et al.; “Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks”; Proceedings of the 36th ACM/IEEE Conference on Design Automation (DAC'99); pp. 831-836.
DINI Group, The; “PCI Hosted, ASIC Prototyping Engine”; DN2000k10; Product Specification; May 2000; available from www.dinigroup.com/products/downloads/dn2k10-314kb.pdf; pp. 1-3.

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