Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1999-06-15
2001-04-24
Phan, Trong (Department: 2818)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
Reexamination Certificate
active
06222386
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to voltage level shifting and more particularly to introducing a variable common-mode DC level offset for a wideband AC signal.
BACKGROUND OF THE INVENTION
Level shift circuits are necessary in digital circuits that belong to high-speed, differential logic families such as emitter coupled logic (ECL) or current mode logic (CML). These circuits provide a wideband solution for obtaining a full diode voltage (Vbe) drop in the common-mode direct current (DC) voltage level of alternating current (AC) input signals. A typical circuit that requires such a level shift circuit is an ECL latch such as that shown in prior art FIG.
1
A. The ECL latch requires a differential AC clock input signals (CLK, CLKX) whose common-mode DC voltage must be shifted down from the common-mode DC voltage of the differential data input signals (D, DX) for proper circuit operation to occur. In particular, for the representative ECL latch shown in
FIG. 1A
, the base to collector junctions of devices connected to the clock inputs CLK and CLKX would be forward biased if the common-mode DC level of the differential clock input signals were not shifted down from the common-mode DC level of the data inputs D and DX. Thus, it becomes necessary to lower the common-mode DC level of the clock input signals CLK and CLKX to a low enough potential to avoid forward biasing the base to collector junctions of the current steering transistors. A variation of the problem where three bias levels are required is shown in FIG.
1
B.
One typical circuit which has been extensively used to lower the common-mode DC level of an AC signal is the emitter follower circuit shown in prior art FIG.
2
. This type of circuit has been developed to lower the common-mode DC voltage level of the clock input signals by an amount equal to a full base to emitter voltage drop for a given bias current. Since the common-mode DC level of the incoming clock signals at terminals INO and INOX is approximately at the supply voltage, the emitter follower circuit lowers the common-mode DC level of the clock signals at terminals O
1
and O
1
X by a full diode drop below the supply voltage. By keeping the input resistance to the level shifting circuit low, the bandwidth of the input signal may be kept relatively constant.
An alternative configuration for obtaining a full diode drop level shift without limiting the input signal's AC bandwidth is shown in prior art FIG.
4
. This approach uses the path through a high-speed differential buffer to maintain high output signal bandwidth. In this approach, a diode connected bipolar transistor is used to drop the differential buffer's supply voltage by a full diode drop or by about 0.9 volts. Thus, the common-mode DC level of the output signals appearing at terminals CLK_OUT and CLK_OUTX is shifted down by a full diode drop from the input signals.
The problem with the full diode drop level shift circuits identified in FIG.
2
and
FIG. 4
is that the present design environment for integrated circuits requires circuit operation in the presence of supply voltages as low as 1.8 volts DC for circuits with two DC bias levels such as the latch in
FIG. 1A. A
similar requirement is for circuits with three bias levels (such as the circuit in
FIG. 1B
) to operate at 2.7 volts. In a contemporary, small-geometry bipolar process, a base to emitter diode voltage drop is approximately 0.9 volts for active devices that are biased for high speed operation. When the supply voltage is lowered to 1.8 volts and the common-mode DC level of the clock input signals is shifted down by 0.9 volts through the use of the full diode drop level shift circuits illustrated in
FIG. 2
or
FIG. 4
, the resulting common-mode DC level of the signals appearing at terminals CLK and CLKX of
FIG. 1A
is 0.9 volts below the 1.8 volt supply voltage, i.e. 0.9 volts. Again, since a base to emitter voltage drop is around 0.9 volts, the DC voltage level present at the emitters of devices Q
2
and Q
3
in
FIG. 1A
will be approximately zero volts.
Thus, the collector to emitter voltage of the current sinking transistor, Q
1
in
FIG. 1A
, will also be approximately zero volts. In the presence of the required bias voltage of around 0.9 volts at the base of transistor Q
1
, the base to collector voltage of Q
1
would be sufficiently high to forward bias this junction, and Q
1
would be in saturation and would not act as a current sink. Therefore, it is not possible to operate digital circuits that belong to high-speed, differential logic families such as emitter coupled logic (ECL) or current mode logic (CML) with traditional full diode drop level shift circuits when operating with supply voltages as low as 1.8 volts. These circuits provide a wideband solution for coupling the outputs of CML logic circuits with the inputs to other logic circuits that require a different DC potential without changing the logic information present at the transmitting circuit output. Thus, the circuit in
FIG. 1A
illustrates the role of the level shift circuit in CML logic.
FIG. 1A
can be treated as a transmitting circuit consisting of a pair of resistors R
1
and R
2
with equal value resistance. One terminal of each resistor is connected to a supply voltage (Vdd). The remaining terminals OUT and OUTX of the resistors are driven by a pair of linked bi-value currents I
1
and I
2
. When I
1
is at value I, I
2
is at value 0. Conversely, if I
2
is at value I, I
1
is at value 0. In this way, a logic signal is defined between terminals OUT and OUTX of the circuit. Logic HIGH is defined when the voltage at terminal OUT is approximately equal to Vdd while the voltage at OUTX is approximately equal to Vdd-Vlogic, where Vlogic is the product of resistor value R and current value I. Logic LOW is defined when the voltage at terminal OUTX is approximately equal to Vdd while the voltage at OUT is approximately equal to Vdd-Vlogic. Typically Vlogic is defined with value sufficiently large to steer substantially all the current in a bipolar diffamp to one collector of the amplifier but small compared to a silicon diode voltage. A typical value is 150 millivolts (mV).
In
FIG. 1B
is a typical receiving circuit illustrating logic with three DC bias levels. The circuit consists of differential amplifiers (devices Q
11
through Q
16
) stacked to form an AND gate. The output voltage is generated by drawing current through differential load resistors R
3
and R
4
. The circuit is biased by source Q
7
with fixed value I. Logic levels at the output are defined in the same manner as in the transmitting circuit. As seen in the figure, output terminal AND is at logic HIGH only when terminal A is at high potential compared to AX, B is at high potential compared to BX and C is at high potential compared to CX.
The need for level shifting the inputs to the receiving circuit is demonstrated by studying the DC voltage constraints at the inputs to the receiving circuit. If the transmitting circuit is coupled to terminals A and AX, acceptable performance can be achieved. If it is assumed that terminals A and AX are excited by a voltage between Vdd and Vdd-Vlogic, application of similar voltages to terminals B and BX results in saturation of devices Q
13
and Q
14
. This results in slow or incorrect circuit operation. Clearly, the DC level of the voltages applied to terminals B and BX must be shifted down with respect to the voltages applied at A and AX by at least Vsat, the minimum voltage applied across a bipolar collector-emitter junction to keep that device from saturating. Similarly, the voltages at terminals C and CX must be below the voltages at B and BX by at least Vsat. At the same time, the logic definitions of the signals must be preserved. For these operations a level-shift circuit is needed.
As discussed above, the problem with the full diode drop level shift circuits identified in FIG.
2
and
FIG. 4
is that the present design environment for integrated circuits requires supply voltages to be minimized. In a contemporary, s
Alford Ronald C.
Martin Frederick L.
Motorola Inc.
Phan Trong
Scutch, III Frank M.
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