Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1996-12-13
1999-09-07
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711157, G06F 1200, G11C 506
Patent
active
059502207
ABSTRACT:
A mapping unit is described for use in a computer system having a multiple bank memory. Each bank of the multiple bank memory includes a plug-in socket defining first and second memory rows. The mapping unit maps a memory control signal for the second row of a first socket adapted to mount one of a single-sided memory element or a double-sided memory element, to the first row of a second socket adapted to mount one of a single-sided memory element or a double-sided memory element, to provide a logical double-sided memory element when single-sided memory elements are plugged into the sockets. A poll routine in the computer system operates to determine the existence of single-sided memory elements in each of the first socket and the second socket, and asserts a select signal when the determination is positive. A multiplexer is provided in the multiple bank memory to receive the select signal from the poll routine and selectively couple the memory control signal for the second row of the first socket to the first row of the second socket, as a function of the select signal.
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patent: 5446691 (1995-08-01), North et al.
patent: 5579277 (1996-11-01), Kelly
patent: 5621678 (1997-04-01), Barnaby et al.
patent: 5765182 (1998-12-01), Lau et al.
Chan Eddie P.
Encarnacion Yamir
Intel Corporation
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