Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-03-31
2000-08-15
Lane, Jack A.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711128, G06F 1200
Patent
active
06105111&
ABSTRACT:
A cache technique for maximizing cache efficiency by assigning ages to elements which access the cache, is described. In one embodiment, the cache technique includes receiving a first element of a first type by a cache and writing the first element in a set of the cache. The first element has a first age. The cache technique further includes receiving a second element of a second type by the cache and writing the second element in the set of the cache. The second element has a middle age, where the first age is a more recently used age than the middle age. In another embodiment, the cache technique includes receiving a first element of a first stream by a cache and writing the first element in a set of the cache. The first element has a first age. The cache technique further includes receiving a second element of a second stream by the cache and writing the second element in the set of the cache. The second element has a middle age, where the first age is a more recently used age than the middle age.
REFERENCES:
patent: 5493667 (1996-02-01), Huck et al.
patent: 5737565 (1998-04-01), Mayfield
Hammarlund Per H.
Hinton Glenn J.
Intel Corporation
Lane Jack A.
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