Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2004-12-30
2009-10-20
Puente, Emerson C (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S718000
Reexamination Certificate
active
07607048
ABSTRACT:
A method and apparatus for protecting a TLB's VPN from soft errors is described. On a TLB lookup, the incoming virtual address is used to CAM the TLB VPN. In parallel with this CAM operation, parity is computed on the incoming virtual address for the possible page sizes supported by the processor. If a matching VPN is found in the TLB, its payload is read out. The encoded page size is used to select which of the set of pre-computed virtual address parity to compare with the stored parity bit in the TLB entry. This has the advantage of removing the computation of parity on the TLB VPN from the critical path of the TLB lookup. Instead it is now in the TLB fill path.
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patent: 7366829 (2008-04-01), Luttrell et al.
patent: 2003/0023932 (2003-01-01), Arndt et al.
patent: 2004/0193992 (2004-09-01), Jamil et al.
Chrysos George Z.
Crawford John H.
Echeruo Ugonna C.
Mukherjee Shubhendu S.
Intel Corporation
McAbee David P.
Puente Emerson C
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