Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Packet header designating cryptographically protected data
Reexamination Certificate
2006-02-07
2006-02-07
Peeso, Thomas R. (Department: 2132)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Packet header designating cryptographically protected data
C713S168000, C713S152000, C713S152000
Reexamination Certificate
active
06996713
ABSTRACT:
Described are methods and circuits of programming a programmable logic device with encrypted configuration data using one or more secure decryption keys. Configurable resources within PLDS in accordance with one embodiment are divided into first and second collections of configurable interconnect resources separated by a collection of switches. One collection of resources has access to one or more decryption keys required to decrypt the encrypted configuration data. The switches protect the proprietary keys by providing a secure boundary around the portion granted key access during the decryption process. Closing the switches after configuration clears user memory to prevent users from accessing stored versions of the proprietary keys.
REFERENCES:
patent: 3849760 (1974-11-01), Endou et al.
patent: 4670749 (1987-06-01), Freeman
patent: 4935737 (1990-06-01), Izbicki et al.
patent: 5084636 (1992-01-01), Yoneda
patent: 5121359 (1992-06-01), Steele
patent: RE34363 (1993-08-01), Freeman
patent: 5237218 (1993-08-01), Josephson et al.
patent: 5237219 (1993-08-01), Cliff
patent: 5256918 (1993-10-01), Suzuki
patent: 5321704 (1994-06-01), Erickson et al.
patent: 5329179 (1994-07-01), Tang et al.
patent: 5341034 (1994-08-01), Matthews
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5349249 (1994-09-01), Chiang et al.
patent: 5388157 (1995-02-01), Austin
patent: 5394031 (1995-02-01), Britton et al.
patent: 5457408 (1995-10-01), Leung
patent: 5598424 (1997-01-01), Erickson et al.
patent: 5768372 (1998-06-01), Sung et al.
patent: 5774544 (1998-06-01), Lee et al.
patent: 5838901 (1998-11-01), Curd et al.
patent: 5914616 (1999-06-01), Young et al.
patent: 5933023 (1999-08-01), Young
patent: 6028445 (2000-02-01), Lawman
patent: 6049222 (2000-04-01), Lawman
patent: 6172520 (2001-01-01), Lawman et al.
patent: RE37195 (2001-05-01), Kean
patent: 0253530 (1987-06-01), None
patent: WO92/20157 (1992-11-01), None
patent: WO94/10754 (1993-11-01), None
patent: WO94/01867 (1994-01-01), None
Xilinx Application Note, “Configuration Issues: Power-Up, Volatility, Security, Battery Back-Up”, By Peter Alfke, XAPP 092, Nov. 24, 1997 (Version 1.1).
Virtex Configuration Guide, published by Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Oct. 9, 2000 (Version 1.0).
Bruce Schneier “Applied Cryptography: Protocols, Algorithms, and Source Code in C”, Second Edition, Copyright 1996, published by John Wiley & Sons, Inc.; Chapter 9, pp. 193-194, Chapter 10, 200-203 and p. 216; Chapter 12, pp. 265-301, Chapter 15, pp. 360-361, p. 456 and 483-502.
Cahners EDN ACCESS Web Page, “Cunning circuits confound crooks,” Oct. 12, 2000; pp. 1-8; http://www.ednmag.com/ednmag/reg/2000/10122000/21df2.htm.
Xilinx, Application Note, XAPP138, “Virtex FPGA Series Configuration an Readback”, published Oct. 4, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Wolfgang Hoflich, Applications Note, “Using the XC4000 Readback Capability”, XAPP 015.000, 1993, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 8-37 to 8-44.
Ann Duncan, Application Note, “DES Encryption and Decryption on the XC6216”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, XAPP 106, Feb. 2, 1998 (version 1.0), pp. 1-7.
“XC9500 In-System Programmable CPLD Family”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Sep. 15, 1999 (version 5.0), pp. 1-16.
Product Specification, “XC18V00 Series of In-System Programmable Configuration PROMs”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Nov. 12, 2001, DS026, (version 3.0), pp. 1-19.
Advanced Product Specification, “XC9500XV Family High-Performance CPLD”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Jan. 15, 2001, DS049, (version 2.0), pp. 1-18.
“The Programmable Logic Data Book”, published 1998, pp. 4-46 through 4-59, available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
“The Programmable Logic Data Book”, published 1994, pp. 2-105, through 2-132, 2-231 through 2-235, available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
Behiel Arthur J.
Peeso Thomas R.
Xilinx , Inc.
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