Method and apparatus for protecting memory-mapped devices from s

Details Method and apparatus for protecting memory-mapped devices from s Method and apparatus for protecting memory-mapped devices from s

1996-12-16

1999-01-26

Coleman, Eric

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711163, G06F 934

Patent

active

058646922

ABSTRACT:
A computer system includes a CPU for executing conventional instructions and speculative instructions, and a memory controller coupled to a system bus. In response to an access operation by one of the instructions, the CPU generates a speculative instruction bit and a corresponding access address. The access address represents a location in a global address space which includes a first address space and a second address space. The speculative instruction bit is asserted when the corresponding access address is generated by a speculative instruction. The memory controller discards the access operation when the speculative instruction bit is asserted and the access address is in the second address space. Thus, the speculative instruction is prevented from accessing the second address space. In one embodiment, the computer system includes a memory coupled to the system bus and mapped to the first address space, and an I/O device coupled to the system bus and mapped to the second address space. The speculative instruction is prevented from accessing the I/O device.

REFERENCES:
patent: 5511172 (1996-04-01), Kimura
patent: 5526499 (1996-06-01), Bernstein
patent: 5623628 (1997-04-01), Brayton
patent: 5640526 (1997-06-01), Mahin
patent: 5708843 (1998-01-01), Abramson

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