Method and apparatus for protecting gate electrodes of target tr

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

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H01L 2362, H01L 2710

Patent

active

061136484

ABSTRACT:
In a gate array having a plurality of free transistors and target transistors, a method and apparatus for protecting a gate electrode of a target transistor from gate charge by employing a free transistor as a gate electrode protection device. A target transistor is a transistor that has been determined to need gate charging protection. A free transistor is a transistor in the gate array which is not used to implement the logic design as embodied in the gate array. Initially, a base array is formed without any metal layers. Then, a determination is made as to which transistors require gate charging protection. The gate electrode of each target transistor determined to require gate charging is coupled to an associated drain or source electrode of a free transistor of the gate array. The gate electrode of the free transistor is connected to an appropriate voltage reference to turn the free transistor off.

REFERENCES:
patent: 5581103 (1996-12-01), Mizukami
patent: 5623420 (1997-04-01), Yee et al.
patent: 5760445 (1998-06-01), Diaz
patent: 5793069 (1998-08-01), Schuelein et al.
patent: 5892379 (1999-04-01), Buxo et al.

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