Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Patent
1997-12-04
2000-04-11
Palys, Joseph E.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
713400, G06F 1100
Patent
active
060498870
ABSTRACT:
A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.
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PCT Search Report for Int'l application PCT/US98/23773 mailed Jul. 8, 1999, 3 pages.
Gadagkar Ashish S.
Khandekar Narendra
Kubick Robert F.
Muthal Manish
VonBokern Vincent E.
Intel Corporation
Palys Joseph E.
Ziemer Rita Ann
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