Method and apparatus for programming and verifying programmable

Details Method and apparatus for programming and verifying programmable Method and apparatus for programming and verifying programmable

1988-08-08

1990-05-29

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

36523009, 365240, G11C 700

Patent

active

049301071

ABSTRACT:
A method and apparatus for programming programmable logic arrays using fewer chip resources is provided. The programmable elements in the programmable logic arrays are serially addressed using shift registers. The method and apparatus are particularly useful in conserving resources on a chip containing several programmable arrays.

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patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4761768 (1988-08-01), Turner et al.

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