Method and apparatus for programming and erasing flash EEPROM me

Static information storage and retrieval – Powering

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36518909, G11C 1300

Patent

active

054146690

ABSTRACT:
An integrated circuit arrangement for providing erase voltages to a flash EEPROM memory array including one charge pump for generating a first high voltage with substantial current which may be used for application to the source terminals of flash EEPROM memory cells during erase and to the gate terminals of flash EEPROM memory cells during programming, and another charge pump for generating a second lower voltage which may be used for application to the drain terminals of flash EEPROM memory cells during programming.

REFERENCES:
patent: 5367489 (1994-11-01), Park et al.

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