Method and apparatus for programmable chip select negation in a

Details Method and apparatus for programmable chip select negation in a Method and apparatus for programmable chip select negation in a

1996-06-06

1999-02-23

Bowler, Alyssa H.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

3958004, 365227, 36523006, G06F 1200

Patent

active

058754822

ABSTRACT:
A data processing system (20) having programmable chip select signal negation. A user programmable "NEGATE EARLY" value generates a chip select negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. Early negation of a chip select signal provides an efficient method of interface with slower devices while providing adding functionality to the chip select signal.

REFERENCES:
patent: 4309754 (1982-01-01), Dinwiddie, Jr.
patent: 4841488 (1989-06-01), Sanada
patent: 5329178 (1994-07-01), Burton
patent: 5688769 (1997-11-01), Coffman et al.

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