Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2002-10-24
2004-12-14
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S459000, C438S977000
Reexamination Certificate
active
06830985
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for producing a bonded dielectric separation wafer, and in more specific, to a method for producing such a bonded dielectric separation wafer having a certain physical relationship established between a position of an orientation flat, “OF”, of a supporting substrate wafer and a position of a pattern of dielectric isolation grooves of an active layer wafer and also to an apparatus used for bonding those wafers.
DESCRIPTION OF THE PRIOR ART
In the prior art, a bonded dielectric separation wafer has been produced through respective steps shown in
FIGS. 5 and 6
.
In one prior art method, at first, a silicon wafer
10
having a mirror-polished surface is fabricated and prepared in accordance with a well-known method, which will be formed into an active layer wafer (see FIG.
5
(
a
)). This silicon wafer
10
has an orientation flat “OF” formed therein. Secondary, a mask oxide film
11
is formed on a surface of this silicon wafer
10
(FIG.
5
(
b
)). Further, after a photo resist
12
is deposited over the mask oxide film
11
, the photo lithography method is applied to form openings in predetermined locations (in apredetermined pattern) thereof. Then, the mask oxide film
11
exposed through these openings is removed so as to form windows of predetermined pattern in the mask oxide film
11
. Consequently, the top surface of the silicon wafer
10
can be partially exposed through these windows. Then, after the photo resist
12
is removed, this silicon wafer
10
is dipped in an alkaline etchant (IPA/KOH/H
2
O) to anisotropically etch the inside of the window defined on the top surface of the wafer (FIG.
5
(
c
)). Through these steps, V-shaped dielectric isolation grooves
13
are formed in the surface of the wafer.
In a subsequent step, this mask oxide film
11
is cleaned and removed using a dilute hydrofluoric acid solution or a buffer hydrofluoric acid solution (FIG.
5
(
d
)). Then, a dielectric separation oxide film
14
is formed on the surface of the silicon wafer
10
through a thermal oxidation processing (FIG.
5
(
e
)). As a result, the dielectric separation oxide film
14
having a predetermined thickness is formed over the surface of the silicon wafer
10
including the surfaces of the dielectric isolation grooves
13
.
Subsequently, this silicon wafer
10
is coated with a seed polysilicon layer
15
over the surface thereof, i.e., over the dielectric separation oxide film
14
, up to a predetermined thickness. After that, a high temperature CVD method is applied at the temperature of about 1200 to 1300° C. so as for a high temperature polysilicon layer
16
to grow over the dielectric separation oxide film
14
until it reaches the thickness of about 150 &mgr;m (FIG.
5
(
f
)). After that, a peripheral portion of this silicon wafer
10
is beveled. In a subsequent step, polishing is applied to a back surface of this silicon wafer
10
so as to remove undesired portion of high temperature polysilicon, which has expanded to cover partially the back surface, thus to obtain a flat surface. Then, grinding and polishing are carried out until the high temperature polysilicon layer
16
on the top surface of the silicon wafer
10
becomes about 10 to 80 &mgr;m thick (FIG.
6
(
g
)).
After that, a low-temperature CVD method is applied at a temperature in the range of 550 to 700° C. so as for a low-temperature polysilicon layer
17
to grow over the surface of the silicon wafer
10
up to 1 to 5 &mgr;m thick. In order to flatten a bonding surface, the top surface of this low-temperature polysilicon layer
17
is mirror-polished (FIG.
6
(
g
)).
On the other hand, a silicon wafer
20
covered with a silicon oxide film
21
is prepared separately from said silicon wafer
10
, which will function as a supporting substrate wafer (FIG.
6
(
h
)). A surface of this silicon wafer
20
has also been mirror-polished. In addition, this silicon wafer
20
has been processed to have the orientation flat.
Then, this silicon wafer
20
is bonded with the other silicon wafer
10
prepared for the active layer wafer as described above, with the mirror-polished surfaces thereof contacting to each other (FIG.
6
(
i
)). Thus, a base material of the bonded wafer has been fabricated.
After that, a thermal processing is applied to thus bonded wafer to enhance its bonding strength.
Then, as shown in FIG.
6
(
j
), the peripheral region of this bonded wafer in the active layer wafer side is beveled. Specifically, the grinding is applied to the bonded wafer from the top surface of the silicon wafer
10
at an oblique angle such that a portion as defined to pass through the bonding interface and to reach the surface layer of the silicon wafer
20
may be cut off.
Then, the top surface of the bonded wafer in the active layer wafer side is ground and further polished (
FIG. 6
(
k
)). The volume to be ground and polished off from the active layer wafer should be determined such that the dielectric separation oxide film
14
may be partially exposed to the outside and thus dielectric separation silicon islands
10
A separated from each other by the dielectric separation oxide film
14
may appear on top of the high temperature polysilicon layer
16
. It is to be noted that the silicon oxide film
21
will be removed by the HF cleaning after the above step.
In this method according to the prior art as discussed above, after the high temperature polysilicon layer
16
having grown on the silicon wafer
10
, the beveling process is applied thereto to remove the polysilicon deposited on the peripheral region of the wafer. However, in practice, it is impossible to carry out this removing process completely, and typically, a part of the polysilicon should be left in the peripheral region of the wafer in order to avoid the reduced diameter of the silicon wafer
10
owing to an excessive grinding.
This means that the polysilicon layers may also be left in the orientation flat (OF) portion of the silicon wafer
10
.
This has often led to such a situation in which after the beveling, the “OF” formed by the residual high temperature polysilicon layer
16
is not in the parallel relationship with the “OF” of the silicon wafer
10
.
Generally, the bonding of the wafers is carried out in such a manner that the “OF” of the active layer wafer and the “OF” of the supporting substrate wafer should be matched and then, in one example, the both wafers are bonded to each other from the central portions toward the peripheral portions thereof so as to increase the bonded area. In this manner, the two wafers can be bonded to each other, while keeping a certain physical relationship between the “OF” of the supporting substrate wafer and the grid pattern of the dielectric isolation grooves formed on the active layer wafer. In specific, the horizontal dielectric isolation grooves or structural elements of the grid pattern in parallel with Y-direction in
FIG. 4
are set to be in parallel with the “OF” of the wafer for the supporting substrate. As a result from this setting, auto-alignment with reference to the “OF” of the supporting substrate wafer will be effective in each consecutive processing step following this bonding step.
However, whether or not this auto-alignment will effectively work depends on the condition of the “OF” portion of the active layer wafer, that the “OF” of the high temperature polysilicon layer should be in parallel with the original “OF” inherent to the active layer wafer. This is because the pattern of the dielectric isolation grooves is externally shielded with the high temperature polysilicon layer and accordingly it would not be possible to bond the supporting substrate wafer to the active layer wafer while visually observing the “OF” of the supporting substrate wafer and the horizontal grooves of said pattern on the active layer wafer and keeping the parallel relationship therebetween on the screen of a monitor, for example. That is, if the “OF” of the high temperature polysilicon layer is not parallel with the “
Oi Hiroyuki
Okuda Hitoshi
Chaudhari Chandra
Kubovcik & Kubovcik
Sumitomo Mitsubishi Silicon Corporation
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