Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
1999-06-14
2002-04-23
Verbrugge, Kevin (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Reexamination Certificate
active
06378030
ABSTRACT:
This application is related to British Patent Application entitled “Video Decompression” as U.K. Serial No. 9405914.4 filed on Mar. 24, 1994 and British Patent Application entitled “Method and Apparatus for Interfacing with RAM” as U.K. Serial No. 9503964.0 filed on Feb. 28, 1995.
BACKGROUND OF THE INVENTION
The present invention relates to random access memory (RAM) and more particularly, to a method for interfacing with RAM.
SUMMARY OF THE INVENTION
The invention provides a RAM interface for connecting a bus to RAM comprising means for receiving from the bus and buffering a plurality of data words, means for receiving from the bus an address associated with the plurality of data words, means for generating a series of addresses in RAM into which the buffered data words will be written, the series of addresses being derived from the received address and means for writing the buffered data words into RAM at the generated address. The data word receiving and buffering means may include a swing buffer. The RAM may operate in a page addressing mode and the address generating means may include means for generating row addresses and means for generating column addresses based on the received address. The RAM may be a DRAM, the bus may include a two wire interface, the data word receiving and buffering means may include a two wire interface, the address receiving means may include a two wire interface and the plurality of data words as well as the received address may be in the form of a token. The RAM interface may further include means for determining whether the data word receiving means has received and buffered the plurality of data words.
The invention also provides a RAM interface for connecting a bus to RAM comprising a plurality of data words stored in RAM at predetermined addresses, means for receiving from the bus a RAM address associated with the plurality of data words, means for generating a series of RAM addresses for addressing the plurality of data words in RAM, the series of addresses being derived from the received address, means for buffering data words read from RAM and means for reading from RAM the plurality of data words, using the series of RAM addresses generated by the address generating means, and writing the data words into buffer means. The data word buffering means may include a swing buffer. The RAM may operate in a page addressing mode and the address generating means may include means for generating row addresses and means for generating column addresses based on the received address. The RAM may be a DRAM, the bus may include a two wire interface, the data word receiving and buffering means may include a two wire interface, the address receiving means may include a two wire interface and the plurality of data words as well as the received address may be in the form of a token. The RAM interface may further include means for determining whether the data word receiving means has received and buffered the plurality of data words.
REFERENCES:
patent: 5138448 (1992-08-01), Gillies et al.
patent: 5227863 (1993-07-01), Bilbrey et al.
patent: 5231605 (1993-07-01), Lee
patent: 5265212 (1993-11-01), Bruce
patent: 5881301 (1999-03-01), Robbins
patent: 5956741 (1999-09-01), Jones
patent: 0468480 (1992-01-01), None
Discovision Associates
Masaki Keiji
Stokey Richard
Verbrugge Kevin
Wong Steve
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