Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-16
2001-04-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S650000, C438S648000, C438S755000, C438S754000, C438S745000
Reexamination Certificate
active
06221766
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor processing and more particularly to method and apparatus for integrated formation of self-aligned refractory metal silicides on silicon substrates.
BACKGROUND AND SUMMARY OF THE INVENTION
Recent improvements in ultra-large scale integration (ULSI) of circuitry on semiconductor substrates indicate that future generations of semiconductor devices will require less than one-quarter micron line widths and spacings with associated higher degrees of cleanliness in the processing of larger wafers using improved processing technologies for more reliable production of more complex devices. One important processing technology currently used in Complementary Metal Oxide Silicon (CMOS) processing technology is the Self-Aligned Silicidation (SALICIDE) of refractory metals such as titanium and cobalt. In a SALICIDE process using cobalt (Co), for example, the source/ drain and polysilicon gate resistances are reduced by forming a high conductivity overlayer and the contact resistance is reduced by increasing the effective contact area. In SALICIDE technology using cobalt silicide (Co Si
2
), a metallic layer of cobalt is sputtered onto the surface of patterned wafers, and desired reactions between cobalt and exposed silicon can be achieved by thermal activation at about 500° C. Unreacted cobalt disposed on a protective layer of silicon oxide can thereafter be selectively etched away, for example, using a solution of sulfuric acid and hydrogen peroxide in a ratio of about 4:1 to yield excellent selectivity of unreacted cobalt relative to reacted cobalt silicide. After such selective etch, thermal annealing at about 700° C. may be used to further reduce the sheet resistance of the remaining silicide regions to about 16-18 &mgr;&OHgr;-cm. Comparable levels of sheet resistance are attained with traditional titanium silicide processing.
The SALICIDE processing technology exploits the principle that a refractory metal such as cobalt deposited on a patterned silicon substrate will selectively react with exposed silicon under specific processing conditions, and will not react with underlying silicon oxide layers. As a result, a selective etch of non-reacted refractory metal results in a maskless, self-aligned formation of a low-resistivity refractory silicide in source, drain, and polysilicon gate regions and in interconnecting conductors of the semiconductor device. In practice, the refractory metal SALICIDE technology includes silicide transformation of deposited refractory metal on silicon via initial rapid thermal processing, or annealing, followed by selective etching away of unreacted refractory metal (typically on oxide regions), followed by a second rapid thermal processing or annealing of the remaining refractory silicide to reduce its resistivity. Improved apparatus and method of annealing and etching are provided for processing semiconductor substrates. Multiple-chamber annealing equipment and liquid etching apparatus are configured to facilitate sequential processing of each of a population of semiconductor wafers to selectively form thereon refractory silicide regions of low resistivity with high resolution in patterns that include thin line widths and narrow line spacings. One or more rapid thermal annealing chambers are integrated with liquid-etch equipment to promote the flow of semiconductor substrates through multiple stages of silicide processing. The liquid-etch equipment includes a rotatable support for a semiconductor substrate for spinning the substrate under a supply of etching solution to thereby chemically remove and physically clean unwanted etch reactants from the surface of the substrate. Automated handling of a substrate through chambers for thermal annealing and liquid etching thus transfer substrates in selected sequences from one supply or input cassette of such substrates, through the processing chambers, to another or output cassette that is positioned to receive each of the processed substrates into individual slots. Such single-wafer processing in selected sequences through the processing equipment facilities shortened processing cycle times for higher throughput of substrates per unit time per configured apparatus, and significantly reduces particulate contamination on substrate surfaces.
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Connolly Bove & Lodge & Hutz LLP
Smith Matthew
Steag RTP Systems, Inc.
Yevsikov V.
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