Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-06-17
2002-04-23
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
C712S221000, C712S244000
Reexamination Certificate
active
06378022
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to a method and apparatus that perform data processing, and, more particularly, to a method and apparatus for processing multi-cycle instructions that may be interrupted during execution.
BACKGROUND
Interrupts are commonly used in data processing systems. For example, interrupts are especially important in many real-time control applications to allow a data processing system to quickly respond to real-time events. The time required for a data processing system to respond to an interrupt is the interrupt latency of the data processing system. A short interrupt latency time allows quick response to interrupts, but may reduce throughput of a data processing system. A long interrupt latency time slows response to interrupts, but may increase throughput of the data processing system. In most data processing systems, it is desirable to have the shortest possible interrupt latency time without reducing the normal operating performance of the data processing system.
Interrupt latency is typically affected by the timing of processor clock boundaries where interrupts are typically sampled. These boundaries occur at the completion of one instruction and the beginning of the next instruction. Multi-cycle instructions increase latency in a data processing system because instruction completion may take many cycles, thereby postponing a boundary where interrupts are sampled. Examples of such instructions are multiply, divide, move multiple memory items and fuzzy logic instructions. The time required to finish executing such instructions before responding to a pending interrupt request may cause the interrupt latency of a data processing system to be too long. The maximum amount of time required for a data processing system to respond to an interrupt, often the time for execution of the longest multi-cycle instruction, determines a data processing system's “maximum interrupt latency time”.
In most data processing systems, it is desirable to minimize the time a data processing system takes to respond to an interrupt. For example, a data processing system which is controlling an automobile engine may receive an interrupt request from the anti-lock braking system when the anti-lock braking system detects that the automobile has entered a skid. In many real-time control applications, a reduction of the maximum interrupt latency time is not only desirable, but also may determine which data processing system is chosen for a particular application. In the example above, if the engine control system cannot respond fast enough to the interrupt from the anti-lock braking system, another data processing system with a shorter interrupt latency time will often be chosen and used.
It is thus very desirable in the data processing field to reduce the maximum interrupt latency time without significantly reducing the normal operating performance of the data processing system. However, many prior systems that reduce interrupt latency also reduce processor throughput. The need to reduce interrupt latency must be balanced with the need to maximize data throughput of a data processing system. Accordingly, there is a need for an improved method and apparatus for processing instructions to reduce or minimize latency while minimally reducing or maintaining processor throughput.
REFERENCES:
patent: 4312066 (1982-01-01), Bantz et al.
patent: 4504903 (1985-03-01), Dickman
patent: 5535380 (1996-07-01), Bergkvist, Jr.
patent: 5794062 (1998-08-01), Baxter
patent: 5889973 (1999-03-01), Moyer
patent: 6178499 (2001-01-01), Stotzer et al.
patent: 6286346 (2001-09-01), Hocken, Jr. et al.
Motorola, Inc. 1992, M68020 User's Manual, Section 7, “Coprocessor Interface Description”, pp. 7-1—7-60.
Intel Pentium Processor Family Developer's Manual vol. 3: Architecture and Programming Manual, 1995, pp. 25/224-233 & 25/266-269.
Fitzsimmons Michael D.
Moyer William C.
Scott Jeffrey W.
Chiu Joanna G.
Hill Susan C.
Lefkowitz Sumati
Motorola Inc.
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