Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-09-04
1999-10-19
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 20, 712 23, 711 5, 711202, G06F 1516
Patent
active
059681608
ABSTRACT:
A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
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Bandoh Tadaaki
Hotta Takashi
Iwamura Masahiro
Kobayashi Yoshiki
Kurosawa Kenichi
An Meng-Ai T.
Davis Jr. Walter D.
Hitachi , Ltd.
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