Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2002-08-22
2004-06-22
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S012000, C714S797000
Reexamination Certificate
active
06754846
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of this invention related to computerized control systems for gathering sensor data from field units and triggering alarms or taking other actions based on the sensor data with respect to such control elements. More particularly this invention relates to multiple processor control units which are synchronized and evaluate sensor data for valid data.
2. Related Art
Many multiple processor control systems are available in the related art. These include systems as typified by U.S. Pat. No. 5,455.914 to Hashemi, et al. includes a multiple module processor which is controlled from a central computer station.
U.S. Pat. No. 4,616,312 to Uebel, describes a two-out-of-three selecting facility in a three-computer system for a Triple Redundant Computer System which is especially suitable for use with microprocessors having a large number of outputs. The computers of the three computer system handle the same processor information in parallel, but exchange their results in an asynchronous manner and compares them.
U.S. Pat. No. 4,627,055 to Mori, et al. describes a decentralized processing method and system having a plurality of subsystems of the same type which are connected to one another. Each subsystem has a diagnostic mean for diagnosis of failure in the other subsystems and functions to take suitable counter-measures.
U.S. Pat. No. 5,239,641 to Horst, for a method and a apparatus for synchronizing a plurality of processors. Each processor runs off its own independent clock, indicates the occurrence of a predescribed processor event on one line and receives signals on another line for initiating a processor wait state.
However, the I/O architecture of the present invention is fundamentally different from prior systems, in that the prior systems rely on intelligent I/O modules, with one microprocessor per leg per module, while the present invention relies on centralized I/O logic, with one microprocessor per leg, controlling all the I/O modules. A degree of local intelligence on each I/O module is implemented through gate array logic, acting primarily as a slave to the main processor. This architecture reduces the component cost and eliminates the significant size of such system which are usually housed in a central location. A unique synchronization system keeps the local clocks in synchronization.
The present invention provides a system which is intended to operate adjacent the equipment being controlled.
SUMMARY OF THE INVENTION
The control system of the present invention comprises a fault tolerant controller, control system platform or computer system having a triple modular redundant (TMR) architecture. The controller consist of three identical channels, except for the power modules which are dual-redundant. Each channel independently executes the application program in parallel with the other two channels. A voting system with voting mechanisms which qualify and verify all digital inputs and outputs from the field; analog inputs are subject to a mid-value selection process.
Each channel is isolated from the others, no single-point failure in any channel can pass to another. If a hardware failure occurs in one channel, the faulty channel is overridden by the other channels. Repair consists of removing and replacing the failed module in the faulty channel while the controller is online and without process interruption.
The controller of the present invention features triplicated main processor modules (MP), input/output modules (I/O) and optionally one or two Local Communications modules (LCM). Each I/O module houses the circuitry for three independent channels. Each channel on the input modules reads the process data and passes that information to its respective MP. The three MP communicate with each other using a high-speed bus called Channel
11
.
The system is a scan based system and once per scan, the MP module synchronizes and communicate with the neighboring MPs over the Channel
11
. The Channel
11
forwards copies of all analog and digital input data to each MP, and compares output data from each MP. The MPs vote the input data, execute the application program and send outputs generated by the application program to the output modules. In addition, the controller votes the output data on the output modules as close to the field as possible to detect and compensate for any errors that could occur between the Channel
11
voting and the final output driven to the field. For each I/O module, the controller can support an option hot-spare module. If present, the hot-spare takes control if a fault is detected on the primary module during operation. The hot-spare position is also used for the online-hot repair of a faulty I/O module.
The MP modules each control a separate channel and operates in parallel with the other two MPs. A dedicated I/O control processor on each MP manages the data exchanged between the MP and the I/O modules. A triplicated I/O bus, located on the base plates, extends from one column of I/O modules to another column of I/O modules using I/O bus cables. In this way the system can be expanded. Each MP poles the appropriate channel of the I/O bus and the I/O bus transmits new input data to the MP on the polling channel. The input data is assembled into a table in the MP and is stored in memory for use in the voting process.
Each input table in each MP is transferred to its neighboring MP over the Channel
11
. After this transfer, voting takes place. The Channel
11
uses a programmable device with a direct memory access to synchronize, transmit, and compare data among the three MPs.
If a disagreement occurs, the signal value found in two of three tables prevails, and the third table is corrected accordingly. Each MP maintains data about necessary correction in local memory. Any disparity is flagged and used at the end of the scan by built-in fault analyzer routines to determine whether a fault exists on a particular module.
The MPs send corrected data to the application program and then executes the application program in parallel with the neighboring MP and generates a table of output values that are based on the table of input values according to user-defined rules. The I/O control processor on each MP manages the transmission of output data to the output modules by means of the I/O bus.
Using the table out output values, the I/O control processor generates smaller tables, each corresponding to an individual output module. Each small table is transmitted to the appropriate channel of the corresponding output module over the I/O bus. For example, MP A transmits the appropriate table to channel A of each output module over the I/O bus A. The transmittal of output data has priority over the routine scanning of all I/O modules.
Each MP provides a 16-megabyte DRAM for the user-written application program, sequence-of-events (SOE) tracking, and I/O data, diagnostics and communication buffers. The application program is stored in flash EPROM and loaded into DRAM for execution. The MPs receive power from redundant 24 VDC power sources. In the event of an external power failure, all critical retentive data is stored in NVRAM. A failure of one power source does not affect controller performance. If the controller loses power, the application program and all critical data are retained.
In addition, each MP can provide direct development and monitoring computer support and Modbus communication Each MP provides one (IEEE 802.3 Ethernet) Development System computer port for downloading the application program to the Trident controller and uploading diagnostic information., one Modbus RE-232/RS-485 serial port which acts as a slave while an external host computer is the master. Typically, a distributed control system (DCS) monitors and optionally updates the controller data directly through an MP.
The triplicated I/O bus is carried baseplate-to-baseplate using Interconnect Assemblies, extender modules, and I/O bus cables. The redundant logic power distribution system is carried using Interconnect Assembli
Gabler John C.
Popp Ronald L.
Rasmussen David C.
Baderman Scott
Cooley & Godward LLP
Invensys Systems Inc.
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