Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-05-02
2004-10-26
Perveen, Rehana (Department: 2116)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S024000, C710S036000, C710S310000, C709S216000
Reexamination Certificate
active
06810448
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a message-based I/O architecture generally and, more particularly, to a method and/or apparatus for processing chain messages.
BACKGROUND OF THE INVENTION
A device driver interfaces a particular hardware device to a specific operating system (OS). The device driver can be split into two modules: one that contains all the OS-specific code and the other for hardware-specific code. The OS-specific module of the device driver can convert operating system calls into I/O transactions. The hardware-specific module of the driver contains vendor-specific code that converts the hardware level interface of the hardware device to the functions required for the particular class of device.
A message-based interface can be used to enable direct message passing between any two device driver modules for a particular class of I/O (message class). Message classes can include (i) LAN ports, such as Ethernet or Token Ring controllers; (ii) random block storage devices, such as hard disk drives and CD-ROM drives; (iii) sequential storage devices and variable block-size devices, such as tape drives; (iv) host bus adapters such as SCSI ports; (v) SCSI devices; (vi) peer data services; (vii) hot plug controller; (viii) IDE controllers and devices; (ix) floppy disk controllers and devices; (x) Fibre Channel; and (xi) WAN ports, such as ATM controllers.
When information is sent to a storage controller, the information frequently does not fit into a single message frame. The information can be split into multiple message frames. When the information is split (segmented) into multiple frames, a “link” or “chain” is needed to re-assemble the information from the multiple message frames.
Conventional hardware and/or firmware solutions traverse a scatter gather list (SGL) to find a “link” or “chain”. The conventional methods for finding the link or chain can require significant processor and hardware overhead. Conventional message chaining is limited to extending SGLs.
SUMMARY OF THE INVENTION
The present invention concerns a message-based I/O architecture comprising a list describing one or more source buffers and a message header. The list may be segmented in multiple memory locations. The message header may be configured to (i) indicate whether the list is segmented and (ii) provide information for linking the list when the list is segmented.
The objects, features and advantages of the present invention include providing a method and apparatus for processing chain messages that may (i) simplify checks for chains for dedicated hardware components and embedded firmware, (ii) provide an indication that a chain exists in a message frame header, and/or (iii) provide a location where chain information is located.
REFERENCES:
patent: 4467411 (1984-08-01), Fry et al.
patent: 5278834 (1994-01-01), Mazzola
patent: 5991797 (1999-11-01), Futral et al.
patent: 6336150 (2002-01-01), Ellis et al.
patent: 6445680 (2002-09-01), Moyal
“Intelligent I/O (12O) Architecture Specification”, Version 1.5, Mar. 1997, pp. 1-1 to 6-127.
“Intelligent I/O (12O) Architecture Specification”, Version 2.0, Mar. 1999, pp. 1-1 to 7-125.
Hoglund Timothy E.
Johnson Stephen B.
Kendall Guy W.
LSI Logic Corporation
Maiorana PC Christopher P.
Perveen Rehana
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