Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor
Reexamination Certificate
1999-11-30
2002-02-26
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
C257S620000
Reexamination Certificate
active
06351022
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a system for processing a planar structure, such as a semiconductor wafer. The invention also relates to a manufacturing method which includes the steps of segmenting a wafer into portions and then reducing the thickness of the segmented portions. The invention also relates to the segmented wafer portions themselves.
In a known manufacturing process, a plurality of integrated circuits are simultaneously patterned and defined on the front surface of a single silicon wafer. The circuits are generally aligned in rows and columns in an orthogonal format. After the circuits are fully defined, the wafer is diced by a sawing machine along lines between the rows and columns to separate the wafer into individual chips. The chips can then be secured within individual packages and/or incorporated into electronic devices.
In the known process, the silicon wafer is sliced from a generally cylindrical ingot. The wafer is at first sliced sufficiently thick enough so as not to warp or break during the formation of the integrated circuits. However, the desired thickness for the finished chips is less than the initial thickness of the sliced wafer. Therefore, after the integrated circuit patterns are defined in the wafer, it has been necessary to grind the back surface of the wafer to reduce its thickness as desired for the finished products.
Grinding machines for grinding down the back surfaces of silicon wafers are known in the art. The known machines have chuck tables for securing a plurality of wafers in position to be ground by one or more grinding wheels. Examples of such grinding machines are illustrated in U.S. Pat. No. 5,679,060 (Leonard), U.S. Pat. No. 4,753,049 (Mori), U.S. Pat. No. 5,632,667 (Earl), and U.S. Pat. No. 5,035,087 (Nishiguchi).
The known wafer processing systems are unsatisfactory, particularly for wafers of relatively large diameter and/or reduced thickness. Recently, silicon wafers having diameters of about thirty centimeters have come into commercial acceptance. These large diameter wafers are prone to breakage and cracking. The tendency of such wafers to break and crack during dicing substantially increases the expense of the fabrication process and reduces process yields. In general, the tendency toward breaking and cracking is proportional to the diameter of the wafer and inversely proportional to its thickness.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method and apparatus wherein semiconductor wafers are segmented into smaller wafer portions prior to grinding.
Another object of the invention is to provide an improved wafer holding table for supporting segmented wafer portions during grinding.
Another object of the invention is to provide a system for producing semiconductor products from large diameter wafers with reduced warpage, breaking and cracking.
Another object of the invention is to provide an economical system for manufacturing integrated circuit chips from brittle semiconductor wafers.
According to one aspect of the invention, semiconductor wafers are segmented prior to being ground, and the segmented wafer portions are supported on a wafer holding table for grinding. By segmenting the wafers before reducing their thickness by grinding, the problem of wafers cracking and breaking during dicing is reduced.
The problem of cracking and breaking is particularly acute for large diameter silicon wafers and for wafers made of group III-V compound semiconductor materials such as GaAs, GaP and InP. The group III-V materials may be more brittle than Si based materials.
According to the present invention, semiconductor wafers may be segmented into various sizes. In a preferred embodiment, the wafers are segmented into quarter-sized segments. In this embodiment, each generally cylindrical wafer is segmented into four pie-shaped portions. In another preferred embodiment, the wafers are diced into individual dies prior to grinding, such that each die contains a single integrated circuit.
The present invention also relates generally to a method of handling planar structures. According to this aspect of the invention, a planar structure is separated into segmented portions, and then the segmented portions are ground down to a desired thickness. In one preferred aspect of the invention, the planar structure is a semiconductor wafer having integrated circuits defined therein.
In another aspect of the invention, a grinding wheel is used to grind down the back surfaces of segmented wafer portions to a desired thickness for packaging and/or further processing.
In another aspect of the invention, wafer portions are secured to a support surface by a vacuum. The vacuum may be applied through regions of porous material. The porous regions may be pie-shaped, like the wafer portions, to efficiently match the contours of the wafer portions.
In another embodiment of the invention, the wafer portions are held in place during grinding by a suitable adhesive material, such as a double sticky film.
The present invention is applicable to a wide variety of materials and products. The invention is not limited to the manufacture of semiconductor products. However, preferred embodiments of the invention are described herein in connection with semiconductor products with integrated circuits, and the invention may be particularly applicable to products formed of relatively brittle semiconductor materials such as GaAs, GaP and InP.
According to one aspect of the invention, finished integrated circuit products are ground down to a thickness of less than about fifteen mils. The present invention is particularly applicable to the manufacture of relatively thin products which would otherwise be prone to breakage and cracking during processing.
These and other objects, features and advantages of the invention will become apparent from the following detailed description of preferred embodiments of the present invention.
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Ball Michael B.
Heppler Steve W.
Clark Jhihan B
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
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