Method and apparatus for prioritizing and routing commands from

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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G06F 1314

Patent

active

060000120

ABSTRACT:
A method and apparatus for prioritizing and routing commands from a command source to a command sink. The command directory receives and stores a command from at least one command source. The data buffer stores the data associated with the command in the allocated portion of the data buffer. Based on status information also stored by the command directory with respect to each command, routing logic in the command directory, corresponding to each command sink, identifies which commands stored in the command buffer to route to the command sink, and routes the identified commands to the command sink. The routing logic also determines a priority of the identified commands and routes the identified commands in order of priority.

REFERENCES:
patent: 5793977 (1998-08-01), Schmidt
Israel, Paul et al, 1995 Electronic Engineering Times (Jun. 19), pp. 78-80, "Chip Set Aims to Speed Secondary Cache--Parallelism Enhances Level 2 Cache Runs".
Jouppi, Norman P., 17th Annual International Symposium on Computer Architecture (May 28-31, 1990) pp. 364-373, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers".
Stiliadis, Dimitrios et al, IEEE Proceedings of the 27th Annual Hawaii International Conference on System Sciences (1994), pp. 412-421, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches".
Stiliadis, Dimitrios et al, IEEE Transactions on Computers, vol. 46, No. 5 (May 1997), pp. 603-610, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches".

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