Method and apparatus for prioritized instruction issue queue...

Details Method and apparatus for prioritized instruction issue queue... Method and apparatus for prioritized instruction issue queue...

2006-04-18

2006-04-18

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S003000, C712S207000

Reexamination Certificate

active

07032101

ABSTRACT:
An apparatus and method in a high performance processor for issuing instructions, comprising; a classification logic for sorting instructions in a number of priority categories, a plurality of instruction queues storing the instruction of differing priorities, and a issue logic selecting from which queue to dispatch instructions for execution. This apparatus and method can be implemented in both in-order, and out-of-order execution processor architectures. The invention also involves instruction cloning, and use of various predictive techniques.

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