Method and apparatus for primary cache tag error handling

Details Method and apparatus for primary cache tag error handling Method and apparatus for primary cache tag error handling

2007-12-18

2007-12-18

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S145000, C711S122000, C711S123000, C714S005110, C714S006130

Reexamination Certificate

active

11100997

ABSTRACT:
A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary cache to the secondary cache. In response to the tag parity packet, each tag entry in the secondary cache that is associated with the parity error is invalidated. Upon receiving an acknowledgment of receipt of the tag parity packet, the primary cache functions to invalidate each tag entry in the primary cache that is associated with the parity error. Then, the secondary cache communicates data requested in the load instruction to the primary cache.

REFERENCES:
patent: 5987579 (1999-11-01), Nishtala et al.
patent: 2002/0087807 (2002-07-01), Gharachorloo et al.
patent: 2003/0208658 (2003-11-01), Magoshi
patent: 2005/0120184 (2005-06-01), Quach et al.
patent: 2006/0010354 (2006-01-01), Azevedo et al.

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