Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-08-16
2003-12-16
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S115000
Reexamination Certificate
active
06665782
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the protection of data stored in digital memory from unauthorized access. The invention is particularly adapted for use in connection with removable non-volatile memory devices such as flash memories and digital film cards.
BACKGROUND OF THE INVENTION
With the proliferation of small, light-weight portable digital devices, such as digital cameras, mp3 players/recorders, digital video cameras, personal digital assistants and other palmtop computing devices, the use of high density, non-volatile, removable memory devices has increased dramatically. Of course, hard disk drives such as those found in personal video recorders, desktop computers and notebook computers, also are high density, non-volatile, digital memories, for storing large volumes of data.
It is often the case that individuals wish to provide enhanced security from unauthorized access for stored data stored in such memory devices. Accordingly, methods and apparatus are known for providing enhanced security. Such methods and apparatus include the use of passwords to gain access to memory devices or portions of memory (e.g., files or directories). Also known are software based encryption systems where the actual bits of the data are stored in memory in a scrambled manner and can only be unscrambled by use of the appropriate encryption key.
U.S. Pat. No. 6,122,716, assigned to the same assignee as the present application, discloses a system and method for authenticating a computer memory having a memory control circuit that scrambles some of the bus lines, thereby scrambling the data in the memory on reset and unscrambles the bus lines responsive to inputs from a lock control circuit. A lock control circuit monitors the bus, waiting for a proper combination of bus values to be asserted onto the bus, at which time the lock control circuit causes the memory control circuit to unscramble the bus lines.
All of the aforementioned schemes are primarily, if not exclusively, software based. It would be useful to have a fully hardware implemented scheme for securing data in memory.
Accordingly, it is an object of the present invention to provide a hardware based method and apparatus for preventing unauthorized access of data stored on a memory.
It is a further object of the present invention to provide an improved method and apparatus for preventing unauthorized access of data stored in memory.
SUMMARY OF THE INVENTION
The invention is applicable to any digital storage medium, such as hard disks, zip drive disks, read only memory (ROM) integrated circuits, but is particularly suitable in connection with removable integrated circuit memories, such as flash memories and digital film cards. In accordance with the invention, the memory device comprises a memory core and a programmable logic circuit, such as a programmable array logic (PAL) circuit, interposed between the memory core and the external terminals (e.g., pins) of the device. The programmable logic circuit preferably is integral with the memory core on a single integrated circuit. A second programmable logic circuit is associated with the data processing device that uses that memory device. The two programmable logic circuits are programmable by the purchaser so that the purchaser can selectively set any external pin of the memory device to couple to any internal memory core signal path such that any chip signal can be assigned to any external pin. The purchaser can program both PALs in a complementary fashion such that the signals have a non-standard, scrambled pin assignment at the physical interface between the memory device and the data processing device, but are descrambled by the two complementary programmed programmable logic circuits at the interface between the programmable logic circuits and the memory core and actual data processing circuitry in the data processing device respectively.
In this manner, the memory device cannot be used with any data processing device that is not equipped with a PAL that is complementarily programmed relative to the PAL of the memory device. Therefore, one having possession of the memory device, but not the data processing device having the complementarily programmed system-side PAL would not be able to read the data out of the memory properly.
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Capps, Jr. Louis Bennie
Daniels Scott Leonard
Neal Danny Marvin
Ng Yat Hung
McBurney Mark
Synnestvedt & Lechner LLP
Verbrugge Kevin
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