Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1998-06-04
1999-03-30
Booth, Richard A.
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
438 15, 438462, 438973, 148DIG162, G01N 3126
Patent
active
058888381
ABSTRACT:
A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.
REFERENCES:
patent: 4333983 (1982-06-01), Allen
patent: 4663890 (1987-05-01), Brandt
patent: 4968628 (1990-11-01), Delgado et al.
patent: 5162241 (1992-11-01), Mori et al.
patent: 5506672 (1996-04-01), Moslehi
patent: 5546797 (1996-08-01), Dutta et al.
Tummala et al., Microelectronics Packaging Handbook-Semiconductor Packing-Part II, Second Edition,, pp. 513-515 , 1997.
Blondin John M.
Brouillette Donald W.
Cook Robert Francis
Diefenderfer David Frederick
Liniger Eric Gerhard
Booth Richard A.
International Business Machines - Corporation
Leas James
Murphy John
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