Method and apparatus for preventing a race condition and maintai

Details Method and apparatus for preventing a race condition and maintai Method and apparatus for preventing a race condition and maintai

1996-08-02

1999-04-06

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711151, 395842, G06F 1318, G06F 1200

Patent

active

058931538

ABSTRACT:
An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA) operations from external IO units and interface with external cache and main memories. The integrated IO system includes an external cache controller that controls access to both the cache and main memory so as to maintain coherency between the cache and main memory. As part of maintaining data coherency, the cache controller prevents race conditions between instructions generated from a core logic unit within the microprocessor and DMA instructions generated from an external IO unit by giving the DMA request priority over the CPU instructions.

REFERENCES:
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5339399 (1994-08-01), Lee et al.
patent: 5553268 (1996-09-01), Willenz et al.
patent: 5557769 (1996-09-01), Bailey et al.
patent: 5655145 (1997-08-01), Chejlava, Jr. et al.

Affiliated with

Also associated with

Rating

Method and apparatus for preventing a race condition and maintai does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for preventing a race condition and maintai, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for preventing a race condition and maintai will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1381965