Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-05-18
2004-12-07
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S166000, C711S167000, C365S229000, C713S001000
Reexamination Certificate
active
06829677
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field:
The present invention relates generally to computer memory and, more particularly, to preserving the contents of synchronous dynamic random access memory during system reset.
2. Description of Related Art:
Usually, when a memory controller is reset, the current state of the memory need not be preserved. However, some design applications require that the contents of memory be preserved during reset so that they can be accessed again after reset. For example, in the case of a hung (i.e., frozen) system, the operator may wish to press the reset button without powering off the system. When the system boots up again, the operator may wish to have the option of querying the contents of the memory in order to try to understand the cause of the previous system hang. Alternatively, the operator may wish to recover data from the memory that was unsaved prior to the system freezing. Of course, in these cases, the boot code would have to provide a means to enter this diagnostic mode before it ever writes to system memory.
One significant problem to overcome in preserving the memory contents in synchronous dynamic random access memory (SDRAM) is maintaining refresh. SDRAM, like other kinds of DRAM, requires refresh cycles to occur with regular frequency. If a certain maximum time, which is dependent upon technology and memory size, is exceeded between refresh cycles, the memory will become corrupted. When a memory controller is reset, all of its internal registers return to their default state. This means that the controller will stop refreshing the memory until it is re-initialized by software. Since the time between the beginning of reset and memory controller re-initialization is variable and will usually be longer than the maximum allowable time between refresh cycles, there is a high probability that memory will become corrupted during this time.
It is not an option to simply exclude the memory controller from seeing certain types of resets. Because a system hang can be caused by countless things, it is necessary to restore all hardware, including the memory controller to their default state during all resets in order to successfully reboot the machine. Since the default state of system memory is random to begin with, preserving its contents will not hinder the reboot process. Therefore, an apparatus and method for adding the functionality of refreshing the memory during certain types of reset signals to new as well as existing architectures is desirable.
SUMMARY OF THE INVENTION
The present invention provides a method, system, and apparatus for maintaining the contents of a self-refreshable memory device during periods of data processing system reset. In one embodiment, a refresh controller receives an indication that the data processing system is being reset. If necessary, the refresh controller modifies the signal from a memory controller to the memory device such that the memory device is placed in a self-refresh mode. The refresh controller keeps the memory device in the self-refresh mode until the data processing system re-enables external refresh signals.
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OptiMagic Inc., “Frequently Asked Questions about Programmable Logic”, © 1997-2001, pp. 1-18.
Attaway David Lawrence
Chetti Leonard F.
Iachetta, Jr. Richard Nicholas
Yong Suksoon
Bataille Pierre-Michel
Carwell Robert M.
International Business Machines - Corporation
Walder, Jr. Stephen J.
Yee Duke W.
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