Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2005-06-21
2005-06-21
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S244000
Reexamination Certificate
active
06910122
ABSTRACT:
Methods and apparatus for stalling a pipeline, which methods and apparatus allow data in speed critical pipeline stages to propagate through additional stages of the pipeline. The data is then “caught” and stored in a deferred stall register as it is output from a downstream pipeline stage X. Finally, the data is output from the deferred stall register in a way that it masks the regular output of the pipeline stage X. In this manner, there is no need to store stalled data in a speed critical pipeline stage. Rather, the data can slip ahead, be saved, and be output at an appropriate time such that it appears that the data was stalled in the pipeline stage in which it existed at the time a stall was initiated.
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Bass Stephen L.
Bhatia Rohit
Gaffin Jeffrey
Knapp Justin
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