Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-01
2003-09-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06615394
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for preparing a simulation model for a semiconductor integrated circuit at power terminals for simulating an electromagnetic interference to the semiconductor integrated circuit, wherein the simulation model is described in a format of variable resistances and load capacitors in order to represent variation in current flowing at power terminal under conditions of constant direct current voltage and variable resistance.
2. Description of the Related Art
Electromagnetic interference appears from a printed circuit board mounted on an electronic device. The main factor of the electromagnetic interference is high frequency currents or radio frequency currents flowing over the printed circuit board, particularly high frequency currents or radio frequency currents from a power terminal of the semiconductor integrated circuit. It is necessary for countermeasure against the electromagnetic interference to estimate the high frequency current flowing through a power layer of the printed circuit board, wherein the estimation is made in the design stage. In order to estimate the high frequency current, it is necessary to use a simulation model for the semiconductor integrated circuit at the power terminal.
A first conventional method of preparing the simulation model for the semiconductor integrated circuit at the power terminal is disclosed in Technical Report Of IEICE EMCJ 99-103 (1999-12) entitled “A New Model Of LSI At Power terminal For EMI Simulation”.
FIG. 1
is a circuit diagram illustrative of a first conventional model for the semiconductor integrated circuit at the power terminal for simulating the electromagnetic interference shown in the above literature.
The first conventional model includes a first power terminal
7
, a second power terminal
8
, a first series connection of a first variable resistance
2
and a second variable resistance
3
between the first and second power terminals
7
and
8
, a second series connection of a first load capacitor
4
and a second load capacitor
5
between the first and second power terminals
7
and
8
, and an internal output terminal
6
. The first and second series connections are parallel to each other between the first and second power terminals
7
and
8
.
The internal output terminal
6
is connected to an intermediate node between the first and second variable resistances
2
and
3
, and also connected to another intermediate node between the first and second load capacitors
4
and
5
. The first variable resistance
2
is connected in series between the internal output terminal
6
and the first power terminal
7
. The second variable resistance
3
is connected in series between the internal output terminal
6
and the second power terminal
8
. The first load capacitor
4
is connected in series between the internal output terminal
6
and the first power terminal
7
. The second load capacitor
5
is connected in series between the internal output terminal
6
and the second power terminal
8
.
Variations in resistances of the first and second variable resistances
2
and
3
result in variations of a first current at the first power terminal
7
and a second current at the second power terminal
8
. The variation of the first current at the first power terminal
7
is used to estimate a first electromagnetic interference from the first power terminal
7
. The variation of the second current at the second power terminal
8
is used to estimate a second electromagnetic interference from the second power terminal
8
.
FIG. 2
is a circuit diagram illustrative of a second conventional model for the semiconductor integrated circuit at the power terminal for simulating the electromagnetic interference shown in the above literature. The second conventional model includes a first power terminal
7
, a second power terminal
8
A a first series connection of a p-channel MOS field effect transistor
38
representing a first variable resistance and a n-channel MOS field effect transistor
39
representing a second variable resistance between the first and second power terminals
7
and
8
, a second series connection of a first load capacitor
4
and a second load capacitor
5
between the first and second power terminals
7
and
8
, and an internal output terminal
6
. The first and second series connections are parallel to each other between the first and second power terminals
7
and
8
.
The internal output terminal
6
is connected to an intermediate node between the p-channel and n-channel MOS field effect transistors
38
and
39
representing first and second variable resistances, and also another intermediate node between the first and second load capacitors
4
and
5
. The p-channel MOS field effect transistor
38
representing the first variable resistance is connected in series between the internal output terminal
6
and the first power terminal
7
. The n-channel MOS field effect transistor
39
representing the second variable resistance is connected in series between the internal output terminal
6
and the second power terminal
8
. The first load capacitor
4
is connected in series between the internal output terminal
6
and the first power terminal
7
. The second load capacitor
5
is connected in series between the internal output terminal
6
and the second power terminal
8
.
A pulse signal generator
37
is connected in series between the second power terminal
8
and gate electrodes of the p-channel and n-channel MOS field effect transistors
38
and
39
. The pulse signal generator
37
generates a pulse signal which is applied to the gate electrodes of the p-channel and n-channel MOS field effect transistors
38
and
39
for controlling ON-OFF operations of the n-channel and n-channel MOS field effect transistors
38
and
39
.
The ON-OFF operations of the p-channel and n-channel MOS field effect transistors
38
and
39
vary first and second variable resistances, resulting in variations of a first current at the first power terminal
7
and a second current at the second power terminal
8
. The variation of the first current at the first power terminal
7
is associated with a first electromagnetic interference at the first power terminal
7
. The variation of the second current at the second power terminal
8
is associated with a second electromagnetic interference at the second power terminal
8
.
FIGS. 3A and 3B
are views of a method of preparing a model for a semiconductor integrated circuit at power terminal for simulating an electromagnetic interference, wherein variable resistances are described by use of transistors From all circuit informations
40
for LSI, only a clock signal system
41
is extracted because a power current of logic based CMOS LSI dominates on the clock signal system. With reference to
FIG. 3B
, all of the transistors and all of the load capacitors operating in the same timing are respectively modeled into a single transistor model and a single load capacitor model, whereby a simulation circuit model
42
is obtained from the clock signal circuit system
41
.
There had not yet been realized a perfect automatic tool for preparing the simulation model of the circuit from the all circuit informations of the semiconductor integrated circuit. This perfect automatic tool needs an extremely high arithmetic processing capability of the computer. In the past, it is manually carried out that the clock signal circuit system is extracted from the huge amount of all data for the all circuit informations of the semiconductor integrated circuit, and then the extracted clock signal circuit system is made into the circuit model for simulation. It is, however, difficult to prepare the variable resistance model described with transistor as shown in FIG.
3
B.
In the above circumstances, it had been required to develop a novel method free from the above problem for preparing a simulation model for a semiconductor integrated circuit at power terminals for simulating an elect
Ogawa Masashi
Wabuka Hiroshi
NEC Corporation
Siek Vuthe
Tat Binh C
Young & Thompson
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