Method and apparatus for prepareing patterns used for...

Details Method and apparatus for prepareing patterns used for... Method and apparatus for prepareing patterns used for...

2006-06-13

2006-06-13

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07062747

ABSTRACT:
A method of preparing layout data of patterns formed in a scribe area. First, library data on which a plurality of patterns and arrangement limiting conditions of each pattern and arrangement importance of each pattern are registered is prepared. A pattern to be arranged in the scribe area is selected from the library data. Then, the selected pattern in the scribe area is arranged in accordance with the arrangement limiting conditions and arrangement importance of the selected pattern. In this method, it is not necessary to prepare many arrangement models, so that preparing time of layout data is shortened.

REFERENCES:
patent: 6467070 (2002-10-01), Kuroda et al.
patent: 6574789 (2003-06-01), Yamauchi
patent: 6694500 (2004-02-01), Toyama
patent: 6763508 (2004-07-01), Igarashi et al.
patent: 2002/0073391 (2002-06-01), Yamauchi et al.
patent: 2003/0027058 (2003-02-01), Kato

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