Method and apparatus for preloading different default address tr

Details Method and apparatus for preloading different default address tr Method and apparatus for preloading different default address tr

1996-12-23

1999-06-29

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711 3, 711205, 395500, 395833, G06F 1200

Patent

active

059182512

ABSTRACT:
A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute storage area, and a preload unit. The translation unit stores translations for translating virtual addresses into physical addresses, and each of these translations includes an attribute field. The default translation attribute storage area stores a number of default translation attributes. The preload unit is coupled to the default translation unit and the translation unit. In response to receiving a signal from the translation unit indicating a translation for a virtual address is not stored in the translation unit, the preload unit transmits the appropriate default translation attribute to the translation unit.

REFERENCES:
patent: 4774659 (1988-09-01), Smith et al.
patent: 4881075 (1989-11-01), Weng
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 5058003 (1991-10-01), White et al.
patent: 5060137 (1991-10-01), Bryg et al.
patent: 5179674 (1993-01-01), Williams et al.
patent: 5278963 (1994-01-01), Hattersley et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5412787 (1995-05-01), Forsyth et al.
patent: 5418975 (1995-05-01), Babaian et al.
patent: 5442766 (1995-08-01), Chu et al.
patent: 5465337 (1995-11-01), Kong
patent: 5475827 (1995-12-01), Lee et al.
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5493660 (1996-02-01), DeLano et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5561814 (1996-10-01), Glew et al.
patent: 5652872 (1997-07-01), Richter et al.
i750, i860, & i960, Processors and Related Products, Intel Corporation (1993) 7 Pages.
Shanley, et al., "ISA System Architecture, New Revised Edition", vol. 1, pp. 137-156 (1991 & 1993).
Kane, et al., "MIPS RISC Architecure", Prentice Hall, Englewood Cliffs, New Jersey, Ch 6, 57 Pages, CH 4, 30 Pages (1992).
PowerPC 601, RISC Microprocessor User's Manual, Memory Management Unit, Ch 6, Motorola, 63 Pages, (1993).
EPO Search Report, Application No. EP 97 30 3535, dated Apr. 8, 1998.

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