Method and apparatus for predictive flash memory erase and...

Details Method and apparatus for predictive flash memory erase and... Method and apparatus for predictive flash memory erase and...

2005-04-12

2005-04-12

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S156000

Reexamination Certificate

active

06880038

ABSTRACT:
A NOR-gate architecture memory with an erase and write time table. The memory processor creates an erase and write time table in a table block. The table contains the most recent times for erase and write operations for each data block in the memory. When a storage operation is initiated, the processor accesses the table and estimates the amount of time it will take to perform the data storage operation and then communicates that back to a host computer. Each data storage operation results in a new table being created that is written into the data block. To save erase and write operations for the table block, the new table is written directly after the most recent table unless there is not enough space. An erase and write operation is only performed on the table block if there is not enough space for the new table.

REFERENCES:
patent: 6125424 (2000-09-01), Komatsu et al.
patent: 6684288 (2004-01-01), Jacobs

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