Method and apparatus for predicting system noise

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system

Reexamination Certificate

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C702S066000, C702S072000, C702S074000, C702S075000, C702S076000, C327S115000, C327S116000, C327S144000, C327S145000, C327S296000, C324S765010

Reexamination Certificate

active

07454301

ABSTRACT:
A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.

REFERENCES:
patent: 5834956 (1998-11-01), Pathikonda et al.
patent: 2003/0132775 (2003-07-01), Yamanaka et al.

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