Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-13
2005-12-13
Lane, Jack (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S137000
Reexamination Certificate
active
06976125
ABSTRACT:
One embodiment of the present invention provides a system for predicting hot spots in a cache memory. Upon receiving a memory operation at the cache, the system determines a target location within the cache for the memory operation. Once the target location is determined, the system increments a counter associated with the target location. If the counter reaches a pre-determined threshold value, the system generates a signal indicating that the target location is a hot spot in the cache memory.
REFERENCES:
patent: 6026475 (2000-02-01), Woodman
patent: 6457139 (2002-09-01), D'Errico et al.
patent: 6874056 (2005-03-01), Dwyer et al.
patent: 2002/0103975 (2002-08-01), Dawkins et al.
Balakrishnan Vijay
Kadambi Sudarshan
Yamamoto Wayne I.
Lane Jack
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
LandOfFree
Method and apparatus for predicting hot spots in cache memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for predicting hot spots in cache memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for predicting hot spots in cache memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3488056