Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-19
2003-03-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S002000, C703S014000
Reexamination Certificate
active
06530064
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to techniques for transistor design and, more specifically, to the determination of a transistor operational lifetime during transistor design.
BACKGROUND OF THE INVENTION
As an integrated circuit is used, the transistors in the integrated circuit may degrade over time and decrease in performance. The length of time before a transistor in an integrated circuit degrades beyond a certain point is referred to as the operational lifetime of the transistor.
As integrated circuits have become increasingly more important in today's society, the complexity of integrated circuits has also increased. The increasing complexity of integrated circuits has led to a need for more efficient analysis of integrated circuits during the design phase. For example, traditional methods of determining the expected operational lifetime of a transistor require fabrication of the transistor and then empirical testing of the transistor. Specifically, traditional methods involve designing a transistor with a view to a desired level of performance, selecting process conditions for fabricating the transistor, fabricating the transistor, and then empirically testing the fabricated transistor to determine its actual performance and operational lifetime. The empirical testing typically takes several days, and the entire procedure, including design, fabrication, and empirical testing of the transistor typically takes several months to complete.
If the actual performance and operational lifetime are not satisfactory, adjustments are made to the fabrication process conditions, or possibly the design itself, and then the entire procedure is repeated. More specifically, the entire process is typically repeated a number of times, until the device design converges to a configuration with satisfactory performance and operational lifetime values. This interative procedure typically requires a large time investment before a design with satisfactory performance and lifetime characteristics is found. It is not unusual for the entire iterative procedure to take a year and a half.
One traditional method of operational lifetime determination includes testing the transistor at operational voltages which are in excess of the normal operational voltage of the transistor, in order to decrease the amount of time required for the transistor to degrade in performance. The change in some characteristic of the transistor is measured at each such operational voltage, and then the normal operational lifetime of the transistor is extrapolated from this data. One such characteristic which is commonly used is the threshold voltage required to turn the transistor on. By plotting the measured operational lifetime for each excessive operational voltage, an operational lifetime for the transistor at a normal operational voltage can be determined by extrapolating it from the curve.
Hypothetically, for example, a transistor with a normal operational voltage of 5 volts may be separately tested at 8 volts and at 7 volts, and the change in threshold voltage over time can be measured for each such voltage. Assume hypothetically that the rate of change in the threshold voltage for an operational voltage of 8 volts is a value which corresponds to a lifetime of 1 hour, and that the rate of change in the threshold voltage for an operational voltage of 7 volts is a value which corresponds to a lifetime of 10 hours. These values and other similar values can then be plotted on a graph, a curve through the plotted points can be determined, and then an operational lifetime for the transistor at an operational voltage of 5 volts can be determined by extrapolating it from the curve connecting the experimental points. A variation of this technique involves plotting lifetime versus the inverse of voltage, because the resulting curve tends to be closer to a straight line, making it easier to use extrapolation to determine a lifetime for a normal operational voltage.
Another traditional technique for determining the operational lifetime of a transistor involves stressing the transistor by applying various gate voltages and measuring the substrate current. There is a gate voltage which induces a maximum or peak substrate current for the transistor, which in turn applies the greatest stress to the transistor under this approach. Measurements made at different gate voltages can be used to plot a curve of lifetime versus gate voltage, which in turn can be used to extrapolate the lifetime that the transistor should have under normal operational conditions.
As evident from the foregoing discussion, it is possible to plot a curve representing the operational lifetime of a transistor versus substrate current. It is known that such a curve can be expressed mathematically by the following equation, where &tgr; is operational lifetime, I
sub
is the substrate current, and A
0
and n are constants.
&tgr;=
A
0
(
I
sub
)
−n
In some cases, the constant n in the foregoing equation may be determined without empirical testing. However, there has been no known technique by which the value of the constant A
0
can be determined, except through empirical testing of an actual transistor having the particular design as to which an operational lifetime is of interest.
From the foregoing discussion, it will be recognized that one of the drawbacks to all traditional methods of determining operational lifetime is that, for any given set of fabrication process conditions for a given transistor design, a transistor must be actually fabricated and then empirically tested in order to determine an operational lifetime for that particular transistor. As discussed above, determining an operational lifetime through empirical testing may take several days. Consequently, since the design of a new transistor and the selection of fabrication process conditions is an iterative procedure that includes a number of cycles, where each cycle involves adjustment, fabrication.and testing/evaluation, and since each evaluation of lifetime requires several days of testing, the overall design procedure from start to finish through several such cycles can be relatively long.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a method and apparatus for accurately predicting an operational lifetime for a new transistor design, without fabricating the new transistor in order to empirically measure the lifetime. According to the present invention, a method and apparatus are provided to address this need, and involve predicting an operational lifetime of a transistor based on design data for the transistor.
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D.Rowlands, S.Dimitrijev and H.B.Harrison “Effect of gate to source / drain junction separation on the device lifetime”,13th Australian Microelectronic Conference. Technology Today for the Future. Proceedings. MICRO'95 pp. 136-140.*
N. Kasai, I. Yamamato, and K. Koyama “Electrical Gate Length Measurement Test Structure for Short Channel MOSFET Characteristics Evaluation”, Proc. IEEE 1995 Int. Conference on Microelectronics Test Structures, vol. 8 Mar. 1995 pp. 39-44.
Amerasekera E. Ajith
Aur Shian-Wei
Burch Richard G.
Davis Joseph C.
Saxena Sharad
Brady III W. James
Dimyan Magid Y
McLarty Peter K.
Siek Vuthe
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