Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
1998-12-31
2002-04-02
Ellis, Richard L. (Department: 2651)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
C712S235000, C712S236000
Reexamination Certificate
active
06367004
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer systems and more particularly to computer system processors that support predication and perform predicate prediction.
BACKGROUND OF THE INVENTION
A processor manipulates and controls the flow of data in a computer system. Increasing the speed or throughput of the processor will tend to increase the computational power of the computer. Processor designers employ many different techniques to increase processor speed and throughput to create more powerful computers for consumers. One technique used by designers is called predication.
Predication is the conditional execution of instructions depending on the value of a predicate. For example, consider the following sequence of instructions:
COMPARE R
1
=R
2
→p
2
(p
2
) ADD R
3
+R
4
→R
5
The first instruction, COMPARE R
1
=R
2
→p
2
, determines a value for the predicate p
2
based on a comparison of the operands R
1
and R
2
. If the value of register R
1
is equal to the value of register R
2
, then the value of predicate p
2
is set to “True”, and if the values of R
1
and R
2
are not equal, then p
2
is set to “False.” “True” and “False” are typically represented in the processor as single bit values “1” and “0”, respectively, (or “0” and “1”, respectively, in a negative logic implementation).
The second instruction, (p
2
) ADD R
3
+R
4
→R
5
, includes two parts. The first part, (p
2
), predicates (or conditions) the second part, ADD R
3
+R
4
→R
5
, on the value of predicate p
2
. If P is true (e.g. a “1”), then the value of R
5
is set equal to the value of R
3
+R
4
. If p
2
is false (e.g. a “0”), then the second part of the instruction is skipped (essentially treating the instruction like a no-op) and the processor executes the next sequential instruction in the program code sequence.
Unfortunately, the COMPARE instruction can take a long time to execute. Because of this, the execution of dependent, subsequent instructions, such as the ADD instruction, may be delayed until the COMPARE instruction completes execution. The present invention address this and other problems.
SUMMARY OF THE INVENTION
A method and apparatus for performing predicate prediction is described. In one method, the least significant bits (LSBs) of a first operand are compared to the LSBs of a second operand. The result of this comparison is used to determine a predicted predicate value for a predicate. A predicated instruction is then conditionally executed depending on the predicted predicate value.
Other features and advantages of the present invention will be apparent from the accompanying figures and the detailed description that follows.
REFERENCES:
patent: 4999800 (1991-03-01), Birger
patent: 5903750 (1999-05-01), Yeh et al.
patent: 6009512 (1999-12-01), Christie
patent: 6021487 (2000-02-01), Maliszewski
patent: 6115808 (2000-09-01), Arora
Tai et al. (Evaluation of a predicate-based software testing strategy) IBM system Journal vol. 33, pp. 445-457, Apr. 12, 1994.
Grochowski Edward T.
Hummel Vincent E.
Mulder Hans J.
Ellis Richard L.
Intel Corporation
Kaplan David J.
Patel Gautam R.
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