Method and apparatus for precharging bitlines in a nonvolatile m

Details Method and apparatus for precharging bitlines in a nonvolatile m Method and apparatus for precharging bitlines in a nonvolatile m

1998-07-27

2000-02-01

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518525, 365203, G11C 700

Patent

active

060210729

ABSTRACT:
A method for precharging a selected bitline (20) in a nonvolatile memory array using a boost circuit (54) in parallel to a pull-up device (22) for biasing the bitline. The boost circuit (54) is controlled by a pulse signal (26). One embodiment uses a regulator circuit (56) to isolate the boost circuit (54) from the bitline when the bitline voltage exceeds a threshold voltage level. The regulator triggers a delay circuit (58) which is coupled to a sense amplifier (60). The delay circuit (58) then defers activation of the sense amplifier (60) until the voltage on the selected bitline (20) is below a sense amplifier threshold voltage level.

REFERENCES:
patent: 4809230 (1989-02-01), Konishi et al.
patent: 5249153 (1993-09-01), Conan
patent: 5671186 (1997-09-01), Igura
patent: 5748536 (1998-05-01), Kwon et al.
patent: 5864511 (1999-01-01), Sato

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