Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-13
2003-01-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06510546
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to configuration of programmable logic devices, and more particularly to design-time routing of run-time reconfigurable circuit designs.
BACKGROUND
Field programmable gate arrays (FPGAs), first introduced by Xilinx in 1985, are becoming increasingly popular devices for use in electronic systems. For example, communications systems employ FPGAS. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
The field of reconfigurable computing has advanced steadily for the past decade, using FPGAs as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic and routing customization at run-time. RTR systems using FPGAs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional FPGA-based systems. However, scarcity of software that supports RTR is believed to be one reason that RTR has been outpaced by research in other areas of reconfigurable computing.
Whereas with traditional configuration of FPGAs the time taken to generate a programming bitstream is generally not real-time critical, with RTR systems, the time required to generate the programming bitstream may be critical from the viewpoint of a user who is waiting for the FPGA to be reconfigured. Thus, it may be acceptable in traditional implementation scenarios to take hours to generate a programming bitstream using traditional configuration methods. In an RTR environment, however, it is expected that the reconfiguration process require no more than a few seconds or even a fraction of a second.
Reconfiguration of an FPGA may include routing and rerouting connections between the logic sections. Routers in a traditional configuration process generally route connections for all the circuit elements. That is, these routers define connections for all the circuit elements in a design, expending a great deal of time in the process. In an RTR environment, traditional routing methods are inappropriate given the real-time operating constraints. Present run-time routing methods provide a great deal of program control over the routing process. For example, the JBits program from Xilinx allows a program to manipulate individual bits in the configuration bitstream for configuring interconnect resources.
The techniques described by Keller, Guccione, and Levi in the patent application entitled, “RUN-TIME ROUTING FOR PROGRAMMABLE LOGIC DEVICES” include programming interfaces that can be called to automatically route from one connection to another. The programming interface, called “JRoute”, alleviates having to write code that routes signals and manipulates individual interconnect resources in a run-time reconfigurable application.
In some instances it may be desirable for a RTR application to include high-level program calls to route connections. For example, if the RTR application contains a black box function which can have many different interfaces, then it would be more desirable to use JRoute to connect the black box to the rest of the design. In general using JBits versus using JRoute is a compromise between speed and flexibility, JBits being faster and JRoute being more flexible. However, for other applications the time spent rerouting with each reconfiguration may be unnecessary.
A method and apparatus that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
SUMMARY OF THE INVENTION
A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDS) are provided in various embodiments of the invention. In one embodiment, run-time parameterizable logic cores are defined in a run-time reconfiguration program, the logic cores having various output pins and input pins. A pre-route tool routes selected ones of the output pins to selected ones of the input pins and generates program code for the run-time reconfiguration program. The program code generated by the pre-route tool programs interconnect resources that make the required connections. The automatically generated program code is then parameterized and included in the run-time reconfiguration program.
Various other embodiments are set forth in the Detailed Description and claims which follow.
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Liu Andrea
Maunu LeRoy D.
Siek Vuthe
Xilinx , Inc.
Young Edel M.
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