Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
1998-12-23
2003-03-25
Ellis, Richard L. (Department: 2655)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S023000, C712S024000
Reexamination Certificate
active
06539471
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of electronic data processing devices. More particularly, the present invention relates to the operation of a data processor.
BACKGROUND
A computer program is composed of a series of ordered instructions that, when executed in a known sequence, bring about a desired result. While in some cases instructions are executed in the order they are arranged in the computer program, in other cases instructions can be executed out-of-order without altering the end result. This characteristic is used by state-of-art computer processors. Such processors employ out-of-order (OOO) processing which allows, in certain cases, for instructions to be executed out-of-order, resulting in greater throughput and better utilization of processing resources.
An OOO processing architecture allows instructions to execute out-of-order or simultaneously, for example, where a later occurring instruction does not substantially employ input data produced from an earlier occurring instruction. However, while instructions may be executed out-of-order if this constraint is met, it remains desirable in many cases that the data produced by instructions executed out-of-order be output, or retired, in a manner that preserves the order of the original instructions. This is true, for example, where the instructions executed out-of-order produce output to the same architectural registers. If a program's proper execution depends on an architectural register to be updated in a certain order in response to executing instructions, it is desirable that the order be preserved whether or not the instructions are to be executed in order. Therefore, processors that implement OOO processing architectures also employ retirement logic that assures that the executed instructions are committed to the architectural registers in the proper order. In one example OOO architecture with retirement logic, a re-order buffer (ROB) holds instructions to be executed by the processor. A reservation station supplies the processor instructions from the ROB, out-of-order in certain cases. The processor executes the instruction, and outputs the result from the executed instruction to the ROB. The ROB in turn retires the executed instructions, in order if required, by committing the result(s) to the architectural registers. Retirement logic, however, introduces delay in processing instructions, and consumes real estate on a processor's semiconductor(s) substrate. Therefore, there is potential value in eliminating the need for retirement logic, or simplifying its operation.
SUMMARY
The present invention provides method and apparatus for reducing or eliminating retirement logic in a processing system. In one embodiment, instructions are grouped for processing so that retirement logic is negligible or not employed. In another embodiment, instructions include retirement stop indications which assist in determining if instructions can be retired without regard to order.
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Ellis Richard L.
Intel Corporation
Patel Gautam R.
LandOfFree
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