Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-10-14
2001-05-15
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185010, C365S185140, C365S185180
Reexamination Certificate
active
06233178
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to flash memory devices. More particularly, the present invention relates to method and apparatus for pre-conditioning the flash memory device to mitigate over-erase induced stresses formed within the device. More specifically this invention relates to flash memory devices where the erase or bulk operation is performed in such a way as to increase the charge stored in the device.
BACKGROUND OF THE INVENTION
A flash memory device is a form of nonvolatile memory that is configured such that a block or sector of memory, typically containing several thousand bits, can be erased as a block and written or programmed on a bit, word, or page basis. The ability to erase a sector of memory at one time allows the device to update (erase and program) relatively quickly.
Flash memory devices may be used for a variety of purposes. For example, flash memory devices may be used in personal computers, digital cellular phones, digital cameras, alarm clocks, and several other devices where it is desirable to store non-volatile information that can be erased and re-programmed.
Generally, flash memory devices include several memory cells, each of which is capable of storing a charge representing a bit. Each cell generally includes a source, a drain, a floating gate, a control gate, and a dielectric material interposed between the floating gate and control gate. Information is stored within the cell by accumulating and/or discharging a charge within the floating gate to change the threshold voltage of the floating gate. For example, the cell may represent a “0” or an erased state when the floating gate is charged, and a “1” or programmed state when the floating gate is discharged.
Generally, each time new information is stored in a sector of memory in a flash memory device, all cells within the sector, whether the cells are in a charged or discharged state, are erased by, for example, submitting all the cells in the sector to a voltage bias to charge all of the floating gates within the cell. After the sector has been erased, information is programmed by discharging desired cells, one at a time, within the device, creating a pattern of binary (“0” and “1”) information. The charge-discharge operation can occur several thousand times in a typical flash memory device during the use of the device over several years.
During typical use of the flash memory devices over a period of time at least some bits may remain in a charged state during each write operation. This is especially true when the data stored in a sector is upgraded with only minor changes to the data. Each time a charged cell (e.g., a cell that was not discharged during a program) is exposed to an erase step, the charge within the floating gate increases. As the charge within the floating gate increases, the voltage potential difference between the control gate (which is at a positive potential during the erase process) and the floating gate (which is at a negative voltage) increases. As the voltage difference between the control gate and the floating gate increases, the dielectric material interposed between the gates becomes stressed. Specifically, as the dielectric material between the floating and control gates is exposed to increasing bias between the two gates, current leakage and dielectric breakdown across the dielectric material becomes increasingly likely. Current leakage, dielectric material breakdown, or a combination thereof allows charges within the floating gate to dissipate. Thus, the storage retention properties of the memory device degrade with current leakage and dielectric material breakdown. Accordingly, a method which mitigates the likelihood of current leakage, dielectric material breakdown, or a combination thereof and a device for implementing such method are desired.
To reduce current leakage and dielectric breakdown, the dielectric thickness may be increased between the floating gate and control gate. However, increasing the dielectric thickness causes manufacturing problems. In particular, as the dielectric thickness increases, the material becomes increasingly difficult to etch to form a desired pattern. In addition, increasing the dielectric material thickness increases the voltage bias required to operate the flash memory device. Increasing the required voltage bias increases the power requirements to operate the flash memory device and reduces the ability to perform continued miniaturization of the memory devices. Such increase in power requirement is undesirable, particularly when the flash memory device is used in portable electronic equipment. Accordingly, an improved device to reduce stress across a dielectric material between a floating gate and a control gate of a flash memory cell that does not require increased dielectric material thickness is desired.
SUMMARY OF THE INVENTION
The present invention provides an improved apparatus and method for programming and erasing flash memory devices. More particularly, the present invention provides a method of pre-conditioning the memory devices to reduce stresses within the devices.
The way in which the present invention addresses the drawbacks of the now-known methods of programming and erasing flash memory devices is discussed in greater detail below. However, in general, the invention includes exposing flash memory cells to a pre-conditioning step prior to erasing the cell. Exposing the cell to a pre-conditioning step mitigates voltage bias buildup between a floating gate and a control gate of the flash memory cell, and thus reduces undesired stresses resulting therefrom.
In accordance with an exemplary embodiment of the present invention, the pre-conditioning step includes exposing the cells to a program or discharge operation. In accordance with an exemplary aspect of this embodiment, an entire sector of flash memory cells are preconditioned at one time. In accordance with a further aspect of this embodiment of the present invention, the pre-conditioning step is performed immediately prior to the erase operation.
In accordance with another exemplary embodiment of the present invention, a device for performing the pre-conditioning step is provided. The device is configured to at least partially discharge all of the flash memory cells within a sector at one time. In accordance with an exemplary aspect of this embodiment, the device operates in embedded mode and does not require external high voltage supplies or other control signals to perform the pre-conditioning step. In accordance with a further aspect of this embodiment, the device supplies a single pulse of current to a sector of flash memory cells.
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Bhattacharya Surya
Das Srinjoy
Gieson Frank Van
Krishnamurthy Shyam
Le Michael
Conexant Systems Inc.
Nguyen Viet Q.
Snell & Wilmer
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