Method and apparatus for powering down the CPU/memory...

Details Method and apparatus for powering down the CPU/memory... Method and apparatus for powering down the CPU/memory...

2006-05-02

2006-05-02

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000

Reexamination Certificate

active

07039755

ABSTRACT:
Power management logic maintains memory in a computer system in the self refresh state during a power savings state in which power is removed from the memory controller. A memory control circuit, separate from the power management logic, controls the memory during other operational modes. The power management logic maintains the system memory in the self refresh state by driving memory control signal(s) at appropriate values during the power savings state.

REFERENCES:
patent: 5630090 (1997-05-01), Keehn et al.
patent: 5940851 (1999-08-01), Leung
patent: 6212599 (2001-04-01), Baweja et al.
patent: 6330639 (2001-12-01), Fanning et al.
patent: 6654895 (2003-11-01), Henkhaus et al.
AMBA Interconnection Schemes, Application Note 05, ARM DAI 0005A, 1998, pp. 1-2, 1-3, and 3-2.
Intel Microsoft Toshiba, “Advanced Configuration and Power Interface Specification”, Revision 1.0b, Feb. 2, 1999, pp. 1-397 (particularly Chapters 1-4).
Samsung Electronics, “DDR SDRAM Specification Version 0.4”, Rev. 0.4 Jul. 1, 1999, pp. 1-49.

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