Method and apparatus for power reduction on a processor bus

Details Method and apparatus for power reduction on a processor bus Method and apparatus for power reduction on a processor bus

2007-03-22

2009-11-24

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S233150

Reexamination Certificate

active

07623396

ABSTRACT:
Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.

REFERENCES:
Blaise Fanning, “Power Control Techniques for Bus Interfaces”, U.S. Appl. No. 11/618,845, filed Dec. 31, 2006.

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