Method and apparatus for power mode transition in a...

Details Method and apparatus for power mode transition in a... Method and apparatus for power mode transition in a...

2005-12-27

2005-12-27

Myers, Paul R. (Department: 2112)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

Reexamination Certificate

active

06981163

ABSTRACT:
A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

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