Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2001-09-12
2004-08-10
Myers, Paul R. (Department: 2112)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
Reexamination Certificate
active
06775786
ABSTRACT:
FIELD
The invention relates to processor power modes. More particularly, the invention relates to a method and apparatus for power mode transition in a multi-thread processor.
BACKGROUND
A processor consumes power as it performs various functions, such as mathematical operations. The amount of power used by the processor will impact, for example, how long a battery in a mobile computer will last. Designers, therefore, have attempted to limit the power used by a processor.
Even when not performing mathematical operations, the generation and distribution of internal clock signals that synchronize the processor's operation will consume a considerable amount of power. To save power, a processor may be designed to operate in a reduced power state when inactive. In the reduced power state, all but a few internal clocks are turned off, which saves power and may extend the life of a battery.
For example, a “sleep” power mode allows most of the internal clocks on a chip to be turned off when the system is idle. A processor may be in the sleep mode, for example, when the system is waiting for an external event, such as the opening of a lid on a laptop computer, or when the computer operating system (OS) is waiting for an Input/Output (I/O) operation.
To aid in energy efficient computing, in some implementations the processor is placed into an even lower power state referred to as a “deep sleep” power mode. The deep sleep mode may be entered, for example, by stopping a clock input signal to the processor after the processor has entered the sleep power mode. This allows the processor to maintain the operational state of elements in the chip, but only draws power equivalent to the processor's leakage current.
With highly complex processors, such as out-of-order processors, some internal “clean-up” may be desired before the internal clocks are disabled. Such clean up is typically performed by micro-code which, for example, cleans up the operational state, drains queues, puts the processor to sleep and waits for an event, or “alarm,” that marks the end of the hibernation.
A “stop grant” power mode, which itself is a low power mode, is typically used for this clean up process. Typically, such a processor transitions from an active mode to the stop grant mode, based on, for example, a pin on the chip being asserted by a “chipset” that controls the processor. When the desired operations have been performed by the micro-code in the processor, the processor sends the chipset an indication, such as a stop grant acknowledge Special Bus Cycle (SBC) over a bus. The chipset may then transition the processor into the sleep and deep sleep modes by, for example, asserting another pin or stopping the bus clock.
SUMMARY
In accordance with an embodiment of the present invention, a first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication-is also issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode.
REFERENCES:
patent: 5367697 (1994-11-01), Barlow et al.
patent: 5515538 (1996-05-01), Kleiman
patent: 5634131 (1997-05-01), Matter et al.
patent: 5655124 (1997-08-01), Lin
patent: 5737615 (1998-04-01), Tetrick
patent: 5813022 (1998-09-01), Ramsey et al.
patent: 5832243 (1998-11-01), Seeman
patent: 6308279 (2001-10-01), Toll et al.
Gunther Stephen H.
Kyker Alan B.
Toll Bret L.
Kenyon & Kenyon
Myers Paul R.
LandOfFree
Method and apparatus for power mode transition in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for power mode transition in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for power mode transition in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3359514