Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-11-04
2002-08-27
Wong, Peter (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S323000
Reexamination Certificate
active
06442698
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to system memory power management in a computer system; more particularly, the present invention relates to power management in memory subsystems.
BACKGROUND OF THE INVENTION
Traditionally, the power generated by memory chips, in particularly, Synchronous Dynamic Random Access Memories (SDRAMs) was of little concern because of the low speeds at which they operate. For example, typical SDRAMs operate at speeds up to 66 Mhz. The power generated by SDRAMs operating at such speeds is relatively low. However, with the increase of the operating speeds of SDRAMs and the advent of the Rambus Dynamic Random Access Memories (RDRAMs), operating speeds have dramatically increased. Presently, SDRAMs are capable of operating at speeds up to 100 Mhz, while RDRAMs operate at clock speeds up to 400 Mhz and transfer rate up to 800 MHz. Memory device operating at such high speed result in a significant amount of power being generated within the device (e.g., on the order of 2.1 watts for RDRAMs). The generation of this magnitude of power may potentially create thermal issues at the memory device.
One current method of remedying the excessive generation of power is by curtailing the bandwidth of a memory. This solution is disadvantageous since it decreases the performance of the memory. Another solution is to use heatsinks and/or cooling fans with memory chips to decrease the heat generated by a memory operating at high speeds. However, this method is disadvantageous because of the cost and amount of space that is consumed by such devices. Therefore, a method and apparatus for managing the power generated by memory chips is desired.
SUMMARY OF THE INVENTION
According to one embodiment, a method of managing power in a memory system is disclosed. The memory system includes multiple memory devices. Each one of the memory devices is grouped in a first group or a second group. First, access to a memory device is requested. It is next determined whether the requested memory device is located in the first group. If the requested memory device is not located within the first group, it is determined whether the first group is filled to capacity. If the first group is not filled to capacity, the requested memory device is transferred to the first group.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Vo Tim
Wong Peter
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