Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-01-07
2004-03-30
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S049130
Reexamination Certificate
active
06715029
ABSTRACT:
FIELD OF THE INVENTION
This invention especially relates to computer and communications systems, including programming and using an associative memory such as, but not limited to a content-addressable memory; and more particularly, the invention relates to possibly decreasing the number of associative memory entries by supplementing an associative memory result with discriminator bits from an original set of information.
BACKGROUND OF THE INVENTION
The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Increasingly, public and private communications networks are being built and expanded using various packet technologies, such as Internet Protocol (IP).
A network device, such as a switch or router, typically receives, processes, and forwards or discards a packet based on one or more criteria, including the type of protocol used by the packet, addresses of the packet (e.g., source, destination, group), and type or quality of service requested. Additionally, one or more security operations are typically performed on each packet. But before these operations can be performed, a packet classification operation must typically be performed on the packet.
Packet classification as required for, inter alia, access control lists (ACLs) and forwarding decisions, is a demanding part of switch and router design. The packet classification of a received packet is increasingly becoming more difficult due to ever increasing packet rates and number of packet classifications. For example, ACLs require matching packets on a subset of fields of the packet flow label, with the semantics of a sequential search through the ACL rules. IP forwarding requires a longest prefix match. Various applications that use packet classification, such as Security Access Control, Quality of Service etc., typically need to perform many matches on source and destination port numbers, protocol and other header fields, etc. Additionally, supporting IPv6 and various tunneling techniques has increased the complexity of packet forwarding. For example, an IPv6 requires 128 bit forwarding and tunneling requires additional bits.
Known approaches of packet classification include using custom application-specific integrated circuits (ASICs), custom circuitry, software or firmware controlled processors, binary and ternary content-addressable memories (CAMs). The use of programmable software or firmware have advantages as they provide some level of flexibility, which becomes especially important as new protocols and services are added to existing network. Customer typically desire to use their existing hardware (e.g., routers, switches etc.) to support these new protocols and services. However, known software and firmware implementations are relatively slow, and typically place a performance bound which may be incompatible with new requirements.
CAMs are increasingly being used in packet classification especially because of their performance. A typical implementation performs a lookup operation on a CAM with the CAM result being used as input to a memory, which produces the actual result used in processing a packet. However, these content-addressable memories are typically expensive in terms of power consumption and space, and are limited in the size of an input word (e.g., 72, 144, etc.) on which a lookup operation is performed. Desired are new methods and apparatus for providing needed matching capabilities, while possibly decreasing the size of an associative memory required or increasing the packet processing capabilities supported by an associative memory.
SUMMARY OF THE INVENTION
Systems and methods are disclosed for possibly decreasing the number of associative memory entries by supplementing an associative memory result with discriminator bits from an original set of information. One embodiment operates on a set of information, the set of information including a lookup word portion and a discriminator portion. A lookup word is derived based on the lookup word portion. A lookup operation is performed on an associative memory, such as, but not limited to a binary or ternary content-addressable memory, using the lookup word to generate an associative memory result. A memory lookup operation is performed on a memory based on the associative memory result and the discriminator portion.
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Freund Dov A.
Goren Gil
Trainin Oded
Chace Christian P.
Sparks Donald
The Law Office of Kirk D. Williams
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