Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-08
2003-07-15
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000
Reexamination Certificate
active
06593227
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for planarizing surfaces of semiconductor device conductive layers and, in one aspect, to a method and apparatus for planarizing such layers via creep strain.
2. Description of the Related Art
Increasing chip density has placed more components on semiconductor wafer surfaces, which in turn, has decreased the area available for surface wiring. The answer to this dilemma has been multilevel metallization schemes and an increased interest in copper conductors. As each layer of copper is deposited, typically via a plating process, the wafer is polished to remove excess copper and planarize the wafer layer. The as-plated surface of the copper layer is irregular, resulting in uneven polishing material removal rates and thus varying polishing times between wafers. Economics of semiconductor device manufacturing require that processes, such as those related to wafer polishing, be continually improved to decrease cost and increase throughput.
Even after polishing, some variations exist in the as-polished surface of copper interconnects due to process variations. These variations may lead to over-polishing in some areas and underpolishing in other areas. Imprecise polishing operations can yield undesirable short circuits or open circuits, which may cause a semiconductor device to operate inconsistently, or not at all.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, an apparatus capable of a process to planarize a surface of a conductive layer on a semiconductor wafer includes a chamber, a holder for holding the semiconductor wafer, and a heating element. The holder is disposed in the chamber and the heating element is capable of heating the conductive layer. The apparatus further includes a temperature measuring element capable of measuring a temperature of the process and a controller capable of controlling the process. The apparatus also includes a heating element controller capable of controlling the heating element. The controller is interconnected with the temperature measuring element and the heating element controller.
A method according to the present invention includes bringing a temperature of the conductive layer to within a predetermined range below a melting point of the conductive layer and holding the temperature of the conductive layer within the predetermined range to allow the conductive layer to undergo strain via at least one creep mechanism due to a weight of the conductive layer. The conductive layer is then cooled.
REFERENCES:
patent: 4410392 (1983-10-01), Winter
patent: 4658362 (1987-04-01), Bhatt
patent: 4915746 (1990-04-01), Welsch
patent: 5976970 (1999-11-01), Dalal et al.
patent: 6404053 (2002-06-01), Givens
D.B. Johnson, et al., “Lateral Diffusion in Ag-Se Thin-Film Couples”, Journal of Applied Physics, vol. 40, No. 1, Jan. 1969, pps. 149-152.
Advanced Micro Devices , Inc.
Ho Hoai
Vu David
Williams Morgan & Amerson P.C.
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