Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-01-05
2001-01-30
Robertson, David L. (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C365S189040
Reexamination Certificate
active
06182189
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices and more particularly to an interface for accessing memories that include hardware read-while-write capabilities.
BACKGROUND OF THE INVENTION
There are many different types of memory devices available today with a wide range of capabilities and operating characteristics. As with many other types of integrated circuit devices, there is a focus on increasing memory device performance, speed, and utility while reducing power consumption or maintaining power consumption at a low level.
Flash memory, an increasingly popular type of memory, is a nonvolatile memory that is electrically erasable and electrically programmable. In many cases, flash memories are now being used for functions traditionally provided by Electrically Erasable Programmable Read Only Memories (EEPROMs) and Static Random Access Memories (SRAMs). Such applications include Basic Input/Output System (BIOS) memories, for example.
There are three basic types of memory access operations that are typically performed in a flash memory: a write (also referred to as program) operation, an erase operation and a read operation.
In currently available flash memories, each of the different memory access operations requires a different amount of time, or latency, to perform. For example, in some current flash memories, a read operation may take approximately 100 nanoseconds to perform, while a program operation may require about 10 microseconds and an erase cycle may take as long as one second to perform.
The difference between the time required for erase and program cycles versus the time required for a read cycle is significant. Therefore, it is advantageous to be able to perform read operations while either program or erase cycles are in process. A flash memory or other memory that provides these capabilities is referred to as a “read-while-write” (RWW) memory.
RWW memories provide increased efficiency along with other advantages. For example, in some prior systems, multiple memory devices are provided such that read and write or program operations can be performed concurrently in order to achieve higher system performance. Using memories that include RWW capability, it may be possible to achieve the same system performance level using fewer memory devices.
Flash memories, like other memories, include an interface that controls operation of the read and write circuitry of the flash memory in response to commands it receives from a processor or other external source. The interface, referred to alternately as a command interface, a user interface, or a command user interface, generally supports a specific set of commands. The supported command set determines, to some extent, the software required to interact with the flash memory.
In some current systems using non-RWW flash memories, if a read request or command is received by a non-RWW flash memory while a write or erase operation is being performed, the read command is not recognized by the flash user interface and may produce an error. For one currently available non-RWW memory, instead of processing the read command, the flash interface controls a flash memory status register to provide status information indicating a status of the write operation being performed. For such a memory, the read command cannot be processed until the write or erase operation is either completed or suspended.
Because of this constraint, if the system cannot tolerate the read/write suspend latency before reading code, then the system may not be able to store both data and code in the same device.
Thus, there is an issue with respect to using existing non-RWW flash memory interfaces for RWW memories.
SUMMARY OF THE INVENTION
An interface method and apparatus for a memory including read-while-write capabilities is described. For one embodiment, a memory device includes a single-chip memory array and an interface responsive to one or more commands to configure the memory array in a read-while-write configuration.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Alexis Ranjeet
Brown Charles W.
Hazen Peter K.
Larsen Robert E.
Faatz Cindy
Intel Corporation
Robertson David L.
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