Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-25
2003-09-23
Crane, Sara (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C326S039000
Reexamination Certificate
active
06625795
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to placement of input/output (I/O) design objects into programmable gate arrays, and more particularly to placement of I/O design objects that use multiple I/O standards or that have different electrical characteristics into a single programmable gate array.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure because of the re-programmability of FPGAs. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
FPGAs generally have logic blocks in the interior of the chip and input/output blocks (IOBs) around the edges of the chip. Recently, FPGAs have been developed that also have IOBs in the interior of the chip. The IOBs send and receive signals off and into the chip and also serve other purposes such as receiving power and ground reference voltages from off the chip. One or more clock signals may also be received for synchronizing signals generated on the chip with other signals off the chip.
The systems in which FPGAs are integrated often have diverse electrical interface characteristics. The increasing capabilities of FPGAs make FPGAs a logical choice for implementing an increasing share of system functionality and interfacing with a variety of devices in the system. Thus, FPGAs have been developed to interface with devices having different electrical interface characteristics. For example, the IOBs of an FPGA, such as Virtex FPGAs from Xilinx, are configurable to operate according to a variety of different I/O standards. Therefore, it is desirable to automatically map a user's input and output design objects to IOBs of the FPGA in a manner that is consistent with the electrical interface requirements.
A method and apparatus that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
The invention provides a method and apparatus for placement of I/O design objects into IOBs of a programmable gate array.
The IOBs of the programmable gate array are arranged in a plurality of banks. The IOBs are configurable to send and receive signals according to a variety of different I/O standards and with a variety of different electrical characteristics. The different I/O standards and electrical characteristics limit which I/O design objects can be placed in the same bank. Only I/O design objects that have “compatible” attributes may be placed together in the same bank. The attributes of an I/O design object define its electrical characteristics and generally depend on the I/O standard used by the I/O design object as well as other criteria. I/O design objects that have compatible attributes are said to be compatible with one another. Compatible I/O design objects can be placed together in the same bank. In one embodiment, sets of compatible I/O design objects are selected. The sets of compatible I/O design objects are then placed into banks while minimizing a placement cost and ensuring that no two I/O design objects having incompatible attributes are placed within a single bank.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
Other aspects and advantages of the invention will become apparent upon seeing the following detailed description and upon reference to the drawings in which:
FIG. 1
is a block diagram of an example FPGA;
FIG. 2
is a flowchart of a method for placement of I/O design objects into IOBs of an FPGA in accordance with an example embodiment of the present invention;
FIG. 3
is a flowchart of an example process for performing a first phase of placement of I/O design objects;
FIG. 4
is a flowchart of a process for bipartite matching of I/O design objects to FPGA IOBs according to an example embodiment of the invention; and
FIG. 5
is a flowchart of an example method for assigning I/O attributes required by a design to banks of an FPGA.
FIG. 6
shows a flowchart of an example method for selecting banks for assignment of compatible I/O attributes.
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Anderson Jason H.
Chari Madabhushi V. R.
Jayaraman Rajeev
Nag Sudip K.
Saunders James L.
Crane Sara
Liu Justin
Maunu LeRoy D.
Xilinx , Inc.
Young Edel M.
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