Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-31
2004-08-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06779169
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of programmable logic devices (PLDs). More specifically, the present relation relates to a method and apparatus for the placement of components onto programmable logic devices.
BACKGROUND
Programmable logic devices (PLDs) may be used to implement large systems that include millions of gates and megabits of embedded memory. The complexity of large systems often require the use of electronic design automation (EDA) tools to manage and optimize their design and placement onto physical target devices. Of the tasks required in managing and optimizing design and placement, satisfying timing constraints of a system is often the most important and the most challenging. In order to satisfy timing constraints, many iterations are often required to determine how components in logic blocks are to be grouped and where these logic blocks are placed on the target device.
Automated placement algorithms in EDA tools perform the time-consuming task of manually mapping logic blocks to physical locations on their target device. However, even state of the art automated algorithms are sometimes incapable of producing solutions that are comparable to user defined manual placement. User defined manual placement techniques are often able to identify critical sections of logic that should be grouped together in order to meet timing constraints that automated algorithms are slow to or even sometimes unable to identify. In addition, many of the state of the art EDA tools utilize a design process that involves the design of modules that make up logic blocks and the integration of the modules into a system before optimizing the system. Systems using this design process may fail to meet performance requirements despite having individual modules that meet the performance requirements before integration. Furthermore, changes made to one module may affect the performance of other modules. Re-optimizing modules to meet system performance requirements often requires additional design iterations which is undesirable.
Thus, what is needed is an improved method and apparatus for design and placement of components on PLDs. This improved method and apparatus should utilize the positive attributes of manual user placement and automated placement of components on PLDs
SUMMARY
A method and apparatus for placement of components of a system onto programmable logic devices (PLDs) is disclosed. The method and apparatus bridges the gap between manual user placement and automated placement of components on PLDs. A user is given the capability to define logic regions that group certain components of the system together. The components may be for example, digital logic, memory devices, or other components. The user may specify a size of a logic region. The user may also specify a location for the logic region. Sizes and/or locations are determined for logic regions having no specified sizes and/or locations. The determined sizes and/or locations allow the system to meet timing constraints. According to an embodiment of the present invention, a user may create logic regions having a hierarchy of arbitrary depth.
A method for positioning components of a system onto a target device utilizing programmable logic devices according to a first embodiment of the present invention is disclosed. A location is determined for a user defined region on the target device that allows the system to satisfy timing constraints.
A method for positioning components of a system onto a target device utilizing programmable logic devices according to a second embodiment of the present invention is disclosed. An optimal size for a user defined region that includes components of the system is determined.
A method for positioning components of a system onto a target device utilizing programmable logic devices according to a third embodiment of the present invention is disclosed. A user is prompted to define a logic region that includes a subset of components of the system to be grouped together. A location is determined for the user defined region on the target device that allows the system to satisfy timing constraints.
A system designed by an electronic design automation (EDA) tool is disclosed. The system includes a first user defined region having a first plurality of components grouped together. The system includes a second user defined region having a second plurality of components grouped together.
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Borer Terry P.
Brown Stephen D.
Quan Gabriel
Sanford Chris
Singh Deshanand P.
Altera Corporation
Cho L.
Levin Naum
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